Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI PIPE3 PHY Module

maintainers:
  - Roger Quadros <rogerq@ti.com>

description:
  The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
  transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
  It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
  interface standard, which defines a common physical layer for
  high-speed serial interfaces.

properties:
  $nodename:
    pattern: "^(pcie-phy|usb3-phy|phy)@[0-9a-f]+$"

  compatible:
    enum:
      - ti,omap-usb3
      - ti,phy-pipe3-pcie
      - ti,phy-pipe3-sata
      - ti,phy-usb3

  reg:
    minItems: 2
    maxItems: 3

  reg-names:
    minItems: 2
    items:
      - const: phy_rx
      - const: phy_tx
      - const: pll_ctrl

  "#phy-cells":
    const: 0

  clocks:
    minItems: 2
    maxItems: 7

  clock-names:
    minItems: 2
    maxItems: 7
    items:
      enum: [wkupclk, sysclk, refclk, dpll_ref,
             dpll_ref_m2, phy-div, div-clk]

  syscon-phy-power:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1
    items:
      items:
        - description: Phandle to the system control module
        - description: Register offset controlling PHY power

  syscon-pllreset:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1
    items:
      items:
        - description: Phandle to the system control module
        - description: Register offset of CTRL_CORE_SMA_SW_0

  syscon-pcs:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1
    items:
      items:
        - description: Phandle to the system control module
        - description: Register offset for PCS delay programming

  ctrl-module:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle of control module for PHY power on.
    deprecated: true

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: ti,phy-pipe3-sata
    then:
      properties:
        syscon-pllreset: true
    else:
      properties:
        syscon-pllreset: false

required:
  - reg
  - compatible
  - reg-names
  - "#phy-cells"
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    /* TI PIPE3 USB3 PHY */
    usb3-phy@4a084400 {
        compatible = "ti,phy-usb3";
        reg = <0x4a084400 0x80>,
              <0x4a084800 0x64>,
              <0x4a084c00 0x40>;
        reg-names = "phy_rx", "phy_tx", "pll_ctrl";
        #phy-cells = <0>;
        clocks = <&usb_phy_cm_clk32k>,
                 <&sys_clkin>,
                 <&usb_otg_ss_refclk960m>;
        clock-names = "wkupclk", "sysclk", "refclk";
        ctrl-module = <&omap_control_usb>;
    };

  - |
    /* TI PIPE3 SATA PHY */
    phy@4a096000 {
        compatible = "ti,phy-pipe3-sata";
        reg = <0x4a096000 0x80>,  /* phy_rx */
              <0x4a096400 0x64>,  /* phy_tx */
              <0x4a096800 0x40>;  /* pll_ctrl */
        reg-names = "phy_rx", "phy_tx", "pll_ctrl";
        clocks = <&sys_clkin1>, <&sata_ref_clk>;
        clock-names = "sysclk", "refclk";
        syscon-pllreset = <&scm_conf 0x3fc>;
        #phy-cells = <0>;
    };
...