Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek XS-PHY Controller

maintainers:
  - Chunfeng Yun <chunfeng.yun@mediatek.com>

description: |
  The XS-PHY controller supports physical layer functionality for USB3.1
  GEN2 controller on MediaTek SoCs.

  Banks layout of xsphy
  ----------------------------------
  port        offset    bank
  u2 port0    0x0000    MISC
              0x0100    FMREG
              0x0300    U2PHY_COM
  u2 port1    0x1000    MISC
              0x1100    FMREG
              0x1300    U2PHY_COM
  u2 port2    0x2000    MISC
              ...
  u31 common  0x3000    DIG_GLB
              0x3100    PHYA_GLB
  u31 port0   0x3400    DIG_LN_TOP
              0x3500    DIG_LN_TX0
              0x3600    DIG_LN_RX0
              0x3700    DIG_LN_DAIF
              0x3800    PHYA_LN
  u31 port1   0x3a00    DIG_LN_TOP
              0x3b00    DIG_LN_TX0
              0x3c00    DIG_LN_RX0
              0x3d00    DIG_LN_DAIF
              0x3e00    PHYA_LN
              ...
  DIG_GLB & PHYA_GLB are shared by U31 ports.

properties:
  $nodename:
    pattern: "^xs-phy@[0-9a-f]+$"

  compatible:
    items:
      - enum:
          - mediatek,mt3611-xsphy
          - mediatek,mt3612-xsphy
          - mediatek,mt7988-xsphy
      - const: mediatek,xsphy

  reg:
    description:
      Register shared by multiple U3 ports, exclude port's private register,
      if only U2 ports provided, shouldn't use the property.
    maxItems: 1

  "#address-cells":
    enum: [1, 2]

  "#size-cells":
    enum: [1, 2]

  ranges: true

  mediatek,src-ref-clk-mhz:
    description:
      Frequency of reference clock for slew rate calibrate
    default: 26

  mediatek,src-coef:
    description:
      Coefficient for slew rate calibrate, depends on SoC process
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 17

# Required child node:
patternProperties:
  "^usb-phy@[0-9a-f]+$":
    type: object
    description:
      A sub-node is required for each port the controller provides.
      Address range information including the usual 'reg' property
      is used inside these nodes to describe the controller's topology.

    properties:
      reg:
        maxItems: 1

      clocks:
        items:
          - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)

      clock-names:
        items:
          - const: ref

      "#phy-cells":
        const: 1
        description: |
          The cells contain the following arguments.

          - description: The PHY type
              enum:
                - PHY_TYPE_USB2
                - PHY_TYPE_USB3

      # The following optional vendor properties are only for debug or HQA test
      mediatek,eye-src:
        description:
          The value of slew rate calibrate (U2 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 7

      mediatek,eye-vrt:
        description:
          The selection of VRT reference voltage (U2 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 7

      mediatek,eye-term:
        description:
          The selection of HS_TX TERM reference voltage (U2 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 7

      mediatek,efuse-intr:
        description:
          The selection of Internal Resistor (U2/U3 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 63

      mediatek,efuse-tx-imp:
        description:
          The selection of TX Impedance (U3 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 31

      mediatek,efuse-rx-imp:
        description:
          The selection of RX Impedance (U3 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 31

      mediatek,syscon-type:
        $ref: /schemas/types.yaml#/definitions/phandle-array
        description:
          A phandle to syscon used to access the register of type switch,
          the field should always be 3 cells long.
        items:
          - items:
              - description:
                  Phandle to phy type configuration system controller
              - description:
                  Phy type configuration register offset
              - description:
                  Index of config segment
                enum: [0, 1, 2, 3]

    required:
      - reg
      - clocks
      - clock-names
      - "#phy-cells"

    additionalProperties: false

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/phy/phy.h>

    u3phy: xs-phy@11c40000 {
        compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
        reg = <0x11c43000 0x0200>;
        mediatek,src-ref-clk-mhz = <26>;
        mediatek,src-coef = <17>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        u2port0: usb-phy@11c40000 {
            reg = <0x11c40000 0x0400>;
            clocks = <&clk48m>;
            clock-names = "ref";
            mediatek,eye-src = <4>;
            #phy-cells = <1>;
        };

        u3port0: usb-phy@11c43000 {
            reg = <0x11c43400 0x0500>;
            clocks = <&clk26m>;
            clock-names = "ref";
            mediatek,efuse-intr = <28>;
            #phy-cells = <1>;
        };
    };

...