Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7110 DMC

maintainers:
  - E Shattow <e@freeshell.de>

description:
  JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at
  2133Mbps (up to 2800Mbps).

properties:
  compatible:
    items:
      - const: starfive,jh7110-dmc

  reg:
    items:
      - description: controller registers
      - description: phy registers

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: pll

  resets:
    items:
      - description: axi
      - description: osc
      - description: apb

  reset-names:
    items:
      - const: axi
      - const: osc
      - const: apb

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/starfive,jh7110-crg.h>
    #include <dt-bindings/reset/starfive,jh7110-crg.h>
    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      memory-controller@15700000 {
        compatible = "starfive,jh7110-dmc";
        reg = <0x0 0x15700000 0x0 0x10000>,
              <0x0 0x13000000 0x0 0x10000>;
        clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
        clock-names = "pll";
        resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
                 <&syscrg JH7110_SYSRST_DDR_OSC>,
                 <&syscrg JH7110_SYSRST_DDR_APB>;
        reset-names = "axi", "osc", "apb";
      };
    };