Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra210 SoC External Memory Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: |
  The EMC interfaces with the off-chip SDRAM to service the request stream
  sent from the memory controller.

properties:
  compatible:
    const: nvidia,tegra210-emc

  reg:
    maxItems: 3

  clocks:
    items:
      - description: external memory clock

  clock-names:
    items:
      - const: emc

  interrupts:
    items:
      - description: EMC general interrupt

  "#interconnect-cells":
    const: 0

  memory-region:
    maxItems: 1
    description:
      phandle to a reserved memory region describing the table of EMC
      frequencies trained by the firmware

  nvidia,memory-controller:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle of the memory controller node

  operating-points-v2:
    description:
      Should contain freqs and voltages and opp-supported-hw property, which
      is a bitfield indicating SoC speedo ID mask.

allOf:
  - $ref: /schemas/thermal/thermal-cooling-devices.yaml

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - nvidia,memory-controller

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    reserved-memory {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        emc_table: emc-table@83400000 {
            compatible = "nvidia,tegra210-emc-table";
            reg = <0x83400000 0x10000>;
        };
    };

    external-memory-controller@7001b000 {
        compatible = "nvidia,tegra210-emc";
        reg = <0x7001b000 0x1000>,
              <0x7001e000 0x1000>,
              <0x7001f000 0x1000>;
        clocks = <&tegra_car TEGRA210_CLK_EMC>;
        clock-names = "emc";
        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
        memory-region = <&emc_table>;
        nvidia,memory-controller = <&mc>;
        operating-points-v2 = <&dvfs_opp_table>;

        #interconnect-cells = <0>;
        #cooling-cells = <2>;
    };