Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml

# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RISC-V Hart-Level Interrupt Controller (HLIC)

description:
  RISC-V cores include Control Status Registers (CSRs) which are local to
  each CPU core (HART in RISC-V terminology) and can be read or written by
  software. Some of these CSRs are used to control local interrupts connected
  to the core. Every interrupt is ultimately routed through a hart's HLIC
  before it interrupts that hart.

  The RISC-V supervisor ISA manual specifies three interrupt sources that are
  attached to every HLIC namely software interrupts, the timer interrupt, and
  external interrupts. Software interrupts are used to send IPIs between
  cores.  The timer interrupt comes from an architecturally mandated real-
  time timer that is controlled via Supervisor Binary Interface (SBI) calls
  and CSR reads. External interrupts connect all other device interrupts to
  the HLIC, which are routed via the platform-level interrupt controller
  (PLIC).

  All RISC-V systems that conform to the supervisor ISA specification are
  required to have a HLIC with these three interrupt sources present.  Since
  the interrupt map is defined by the ISA it's not listed in the HLIC's device
  tree entry, though external interrupt controllers (like the PLIC, for
  example) will need to define how their interrupts map to the relevant HLICs.
  This means a PLIC interrupt property will typically list the HLICs for all
  present HARTs in the system.

maintainers:
  - Palmer Dabbelt <palmer@dabbelt.com>
  - Paul Walmsley <paul.walmsley@sifive.com>

properties:
  compatible:
    oneOf:
      - items:
          - const: andestech,cpu-intc
          - const: riscv,cpu-intc
      - const: riscv,cpu-intc

  interrupt-controller: true

  '#interrupt-cells':
    const: 1
    description: |
      The interrupt sources are defined by the RISC-V supervisor ISA manual,
      with only the following three interrupts being defined for
      supervisor mode:
        - Source 1 is the supervisor software interrupt, which can be sent by
          an SBI call and is reserved for use by software.
        - Source 5 is the supervisor timer interrupt, which can be configured
          by SBI calls and implements a one-shot timer.
        - Source 9 is the supervisor external interrupt, which chains to all
          other device interrupts.

required:
  - compatible
  - '#interrupt-cells'
  - interrupt-controller

additionalProperties: false

examples:
  - |
    interrupt-controller {
        #interrupt-cells = <1>;
        compatible = "riscv,cpu-intc";
        interrupt-controller;
    };