| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| %YAML 1.2 | |
| --- | |
| $id: http://devicetree.org/schemas/dma/intel,ldma.yaml# | |
| $schema: http://devicetree.org/meta-schemas/core.yaml# | |
| title: Lightning Mountain centralized DMA controllers. | |
| maintainers: | |
| - chuanhua.lei@intel.com | |
| - mallikarjunax.reddy@intel.com | |
| allOf: | |
| - $ref: dma-controller.yaml# | |
| properties: | |
| compatible: | |
| enum: | |
| - intel,lgm-cdma | |
| - intel,lgm-dma2tx | |
| - intel,lgm-dma1rx | |
| - intel,lgm-dma1tx | |
| - intel,lgm-dma0tx | |
| - intel,lgm-dma3 | |
| - intel,lgm-toe-dma30 | |
| - intel,lgm-toe-dma31 | |
| reg: | |
| maxItems: 1 | |
| "#dma-cells": | |
| const: 3 | |
| description: | |
| The first cell is the peripheral's DMA request line. | |
| The second cell is the peripheral's (port) number corresponding to the channel. | |
| The third cell is the burst length of the channel. | |
| dma-channels: | |
| minimum: 1 | |
| maximum: 16 | |
| dma-channel-mask: | |
| maxItems: 1 | |
| clocks: | |
| maxItems: 1 | |
| resets: | |
| maxItems: 1 | |
| reset-names: | |
| items: | |
| - const: ctrl | |
| interrupts: | |
| maxItems: 1 | |
| intel,dma-poll-cnt: | |
| $ref: /schemas/types.yaml#/definitions/uint32 | |
| description: | |
| DMA descriptor polling counter is used to control the poling mechanism | |
| for the descriptor fetching for all channels. | |
| intel,dma-byte-en: | |
| type: boolean | |
| description: | |
| DMA byte enable is only valid for DMA write(RX). | |
| Byte enable(1) means DMA write will be based on the number of dwords | |
| instead of the whole burst. | |
| intel,dma-drb: | |
| type: boolean | |
| description: | |
| DMA descriptor read back to make sure data and desc synchronization. | |
| intel,dma-dburst-wr: | |
| type: boolean | |
| description: | |
| Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst; | |
| if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16. | |
| It only applies to RX DMA and memcopy DMA. | |
| required: | |
| - compatible | |
| - reg | |
| additionalProperties: false | |
| examples: | |
| - | | |
| dma0: dma-controller@e0e00000 { | |
| compatible = "intel,lgm-cdma"; | |
| reg = <0xe0e00000 0x1000>; | |
| #dma-cells = <3>; | |
| dma-channels = <16>; | |
| dma-channel-mask = <0xFFFF>; | |
| interrupt-parent = <&ioapic1>; | |
| interrupts = <82 1>; | |
| resets = <&rcu0 0x30 0>; | |
| reset-names = "ctrl"; | |
| clocks = <&cgu0 80>; | |
| intel,dma-poll-cnt = <4>; | |
| intel,dma-byte-en; | |
| intel,dma-drb; | |
| }; | |
| - | | |
| dma3: dma-controller@ec800000 { | |
| compatible = "intel,lgm-dma3"; | |
| reg = <0xec800000 0x1000>; | |
| clocks = <&cgu0 71>; | |
| resets = <&rcu0 0x10 9>; | |
| #dma-cells = <3>; | |
| intel,dma-poll-cnt = <16>; | |
| intel,dma-byte-en; | |
| intel,dma-dburst-wr; | |
| }; |