| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| %YAML 1.2 | |
| --- | |
| $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml# | |
| $schema: http://devicetree.org/meta-schemas/core.yaml# | |
| title: NVIDIA Tegra ISP processor | |
| maintainers: | |
| - Thierry Reding <thierry.reding@gmail.com> | |
| - Jon Hunter <jonathanh@nvidia.com> | |
| properties: | |
| compatible: | |
| oneOf: | |
| - enum: | |
| - nvidia,tegra20-isp | |
| - nvidia,tegra30-isp | |
| - nvidia,tegra114-isp | |
| - nvidia,tegra124-isp | |
| - nvidia,tegra210-isp | |
| - items: | |
| - const: nvidia,tegra132-isp | |
| - const: nvidia,tegra124-isp | |
| reg: | |
| maxItems: 1 | |
| interrupts: | |
| maxItems: 1 | |
| clocks: | |
| items: | |
| - description: module clock | |
| resets: | |
| items: | |
| - description: module reset | |
| reset-names: | |
| items: | |
| - const: isp | |
| iommus: | |
| maxItems: 1 | |
| interconnects: | |
| items: | |
| - description: memory write client | |
| interconnect-names: | |
| items: | |
| - const: dma-mem # write | |
| power-domains: | |
| items: | |
| - description: phandle to the VENC or core power domain | |
| additionalProperties: false | |
| examples: | |
| - | | |
| #include <dt-bindings/clock/tegra20-car.h> | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| isp@54100000 { | |
| compatible = "nvidia,tegra20-isp"; | |
| reg = <0x54100000 0x00040000>; | |
| interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&tegra_car TEGRA20_CLK_ISP>; | |
| resets = <&tegra_car 23>; | |
| reset-names = "isp"; | |
| }; |