| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| %YAML 1.2 | |
| --- | |
| $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# | |
| $schema: http://devicetree.org/meta-schemas/core.yaml# | |
| title: MSM Display Port Controller | |
| maintainers: | |
| - Kuogee Hsieh <quic_khsieh@quicinc.com> | |
| - Abhinav Kumar <quic_abhinavk@quicinc.com> | |
| description: | | |
| Device tree bindings for DisplayPort host controller for MSM targets | |
| that are compatible with VESA DisplayPort interface specification. | |
| properties: | |
| compatible: | |
| oneOf: | |
| - enum: | |
| - qcom,glymur-dp | |
| - qcom,sa8775p-dp | |
| - qcom,sc7180-dp | |
| - qcom,sc7280-dp | |
| - qcom,sc7280-edp | |
| - qcom,sc8180x-dp | |
| - qcom,sc8180x-edp | |
| - qcom,sc8280xp-dp | |
| - qcom,sc8280xp-edp | |
| - qcom,sdm845-dp | |
| - qcom,sm8350-dp | |
| - qcom,sm8650-dp | |
| - qcom,x1e80100-dp | |
| - items: | |
| - enum: | |
| - qcom,qcs8300-dp | |
| - const: qcom,sa8775p-dp | |
| - items: | |
| - enum: | |
| - qcom,sm6350-dp | |
| - const: qcom,sc7180-dp | |
| # deprecated entry for compatibility with old DT | |
| - items: | |
| - enum: | |
| - qcom,sm6350-dp | |
| - const: qcom,sm8350-dp | |
| deprecated: true | |
| - items: | |
| - enum: | |
| - qcom,sar2130p-dp | |
| - qcom,sm7150-dp | |
| - qcom,sm8150-dp | |
| - qcom,sm8250-dp | |
| - qcom,sm8450-dp | |
| - qcom,sm8550-dp | |
| - const: qcom,sm8350-dp | |
| - items: | |
| - enum: | |
| - qcom,sm6150-dp | |
| - const: qcom,sm8150-dp | |
| - const: qcom,sm8350-dp | |
| - items: | |
| - enum: | |
| - qcom,eliza-dp | |
| - qcom,sm8750-dp | |
| - const: qcom,sm8650-dp | |
| reg: | |
| minItems: 4 | |
| items: | |
| - description: ahb register block | |
| - description: aux register block | |
| - description: link register block | |
| - description: p0 register block | |
| - description: p1 register block | |
| - description: p2 register block | |
| - description: p3 register block | |
| - description: mst2link register block | |
| - description: mst3link register block | |
| interrupts: | |
| maxItems: 1 | |
| clocks: | |
| minItems: 5 | |
| items: | |
| - description: AHB clock to enable register access | |
| - description: Display Port AUX clock | |
| - description: Display Port Link clock | |
| - description: Link interface clock between DP and PHY | |
| - description: Display Port stream 0 Pixel clock | |
| - description: Display Port stream 1 Pixel clock | |
| - description: Display Port stream 2 Pixel clock | |
| - description: Display Port stream 3 Pixel clock | |
| clock-names: | |
| minItems: 5 | |
| items: | |
| - const: core_iface | |
| - const: core_aux | |
| - const: ctrl_link | |
| - const: ctrl_link_iface | |
| - const: stream_pixel | |
| - const: stream_1_pixel | |
| - const: stream_2_pixel | |
| - const: stream_3_pixel | |
| phys: | |
| maxItems: 1 | |
| phy-names: | |
| items: | |
| - const: dp | |
| operating-points-v2: true | |
| opp-table: | |
| type: object | |
| power-domains: | |
| maxItems: 1 | |
| aux-bus: | |
| $ref: /schemas/display/dp-aux-bus.yaml# | |
| data-lanes: | |
| $ref: /schemas/types.yaml#/definitions/uint32-array | |
| deprecated: true | |
| minItems: 1 | |
| maxItems: 4 | |
| items: | |
| maximum: 3 | |
| "#sound-dai-cells": | |
| const: 0 | |
| vdda-0p9-supply: | |
| deprecated: true | |
| vdda-1p2-supply: | |
| deprecated: true | |
| ports: | |
| $ref: /schemas/graph.yaml#/properties/ports | |
| properties: | |
| port@0: | |
| $ref: /schemas/graph.yaml#/properties/port | |
| description: Input endpoint of the controller | |
| port@1: | |
| $ref: /schemas/graph.yaml#/$defs/port-base | |
| unevaluatedProperties: false | |
| description: Output endpoint of the controller | |
| properties: | |
| endpoint: | |
| $ref: /schemas/media/video-interfaces.yaml# | |
| unevaluatedProperties: false | |
| properties: | |
| data-lanes: | |
| minItems: 1 | |
| maxItems: 4 | |
| items: | |
| enum: [ 0, 1, 2, 3 ] | |
| link-frequencies: | |
| minItems: 1 | |
| maxItems: 4 | |
| items: | |
| enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ] | |
| required: | |
| - port@0 | |
| - port@1 | |
| required: | |
| - compatible | |
| - reg | |
| - interrupts | |
| - clocks | |
| - clock-names | |
| - phys | |
| - phy-names | |
| - power-domains | |
| - ports | |
| allOf: | |
| # AUX BUS does not exist on DP controllers | |
| # Audio output also is present only on DP output | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - qcom,sc7280-edp | |
| - qcom,sc8180x-edp | |
| - qcom,sc8280xp-edp | |
| then: | |
| properties: | |
| "#sound-dai-cells": false | |
| else: | |
| if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - qcom,glymur-dp | |
| - qcom,sa8775p-dp | |
| - qcom,x1e80100-dp | |
| then: | |
| $ref: /schemas/sound/dai-common.yaml# | |
| oneOf: | |
| - required: | |
| - aux-bus | |
| - required: | |
| - "#sound-dai-cells" | |
| else: | |
| $ref: /schemas/sound/dai-common.yaml# | |
| properties: | |
| aux-bus: false | |
| required: | |
| - "#sound-dai-cells" | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| # these platforms support SST only | |
| - qcom,sc7180-dp | |
| - qcom,sc7280-dp | |
| - qcom,sc7280-edp | |
| - qcom,sc8180x-edp | |
| - qcom,sc8280xp-edp | |
| then: | |
| properties: | |
| reg: | |
| minItems: 5 | |
| maxItems: 5 | |
| clocks: | |
| minItems: 5 | |
| maxItems: 5 | |
| clock-names: | |
| minItems: 5 | |
| maxItems: 5 | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| # these platforms support 2 streams MST on some interfaces, | |
| # others are SST only | |
| - qcom,sc8280xp-dp | |
| - qcom,x1e80100-dp | |
| then: | |
| properties: | |
| reg: | |
| minItems: 5 | |
| maxItems: 5 | |
| clocks: | |
| minItems: 5 | |
| maxItems: 6 | |
| clock-names: | |
| minItems: 5 | |
| maxItems: 6 | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| # 2 streams MST | |
| enum: | |
| - qcom,sc8180x-dp | |
| - qcom,sdm845-dp | |
| - qcom,sm8350-dp | |
| then: | |
| properties: | |
| reg: | |
| minItems: 5 | |
| maxItems: 5 | |
| clocks: | |
| minItems: 6 | |
| maxItems: 6 | |
| clock-names: | |
| minItems: 6 | |
| maxItems: 6 | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - qcom,sm8650-dp | |
| then: | |
| properties: | |
| reg: | |
| minItems: 5 | |
| maxItems: 9 | |
| clocks: | |
| minItems: 6 | |
| maxItems: 6 | |
| clocks-names: | |
| minItems: 6 | |
| maxItems: 6 | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| # these platforms support 4 stream MST on first DP, | |
| # 2 streams MST on the second one. | |
| - qcom,sa8775p-dp | |
| then: | |
| properties: | |
| reg: | |
| minItems: 9 | |
| maxItems: 9 | |
| clocks: | |
| minItems: 6 | |
| maxItems: 8 | |
| clock-names: | |
| minItems: 6 | |
| maxItems: 8 | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| # these platforms support 2 streams MST on some interfaces, | |
| # others are SST only, but all controllers have 4 ports | |
| - qcom,glymur-dp | |
| then: | |
| properties: | |
| reg: | |
| minItems: 9 | |
| maxItems: 9 | |
| clocks: | |
| minItems: 5 | |
| maxItems: 6 | |
| clock-names: | |
| minItems: 5 | |
| maxItems: 6 | |
| unevaluatedProperties: false | |
| examples: | |
| - | | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| #include <dt-bindings/clock/qcom,dispcc-sc7180.h> | |
| #include <dt-bindings/power/qcom-rpmpd.h> | |
| displayport-controller@ae90000 { | |
| compatible = "qcom,sc7180-dp"; | |
| reg = <0xae90000 0x200>, | |
| <0xae90200 0x200>, | |
| <0xae90400 0xc00>, | |
| <0xae91000 0x400>, | |
| <0xae91400 0x400>; | |
| interrupt-parent = <&mdss>; | |
| interrupts = <12>; | |
| clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, | |
| <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, | |
| <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, | |
| <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, | |
| <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; | |
| clock-names = "core_iface", "core_aux", | |
| "ctrl_link", | |
| "ctrl_link_iface", "stream_pixel"; | |
| assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, | |
| <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; | |
| assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; | |
| phys = <&dp_phy>; | |
| phy-names = "dp"; | |
| #sound-dai-cells = <0>; | |
| power-domains = <&rpmhpd SC7180_CX>; | |
| ports { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| port@0 { | |
| reg = <0>; | |
| endpoint { | |
| remote-endpoint = <&dpu_intf0_out>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <1>; | |
| endpoint { | |
| remote-endpoint = <&typec>; | |
| data-lanes = <0 1>; | |
| link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| ... |