| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| %YAML 1.2 | |
| --- | |
| $id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml# | |
| $schema: http://devicetree.org/meta-schemas/core.yaml# | |
| title: Mediatek display overdirve | |
| maintainers: | |
| - Chun-Kuang Hu <chunkuang.hu@kernel.org> | |
| - Philipp Zabel <p.zabel@pengutronix.de> | |
| description: | | |
| Mediatek display overdrive, namely OD, increases the transition values | |
| of pixels between consecutive frames to make LCD rotate faster. | |
| OD device node must be siblings to the central MMSYS_CONFIG node. | |
| For a description of the MMSYS_CONFIG binding, see | |
| Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | |
| for details. | |
| properties: | |
| compatible: | |
| oneOf: | |
| - enum: | |
| - mediatek,mt2712-disp-od | |
| - mediatek,mt8173-disp-od | |
| - items: | |
| - const: mediatek,mt6795-disp-od | |
| - const: mediatek,mt8173-disp-od | |
| reg: | |
| maxItems: 1 | |
| interrupts: | |
| maxItems: 1 | |
| clocks: | |
| items: | |
| - description: OD Clock | |
| ports: | |
| $ref: /schemas/graph.yaml#/properties/ports | |
| description: | |
| Input and output ports can have multiple endpoints, each of those | |
| connects to either the primary, secondary, etc, display pipeline. | |
| properties: | |
| port@0: | |
| $ref: /schemas/graph.yaml#/properties/port | |
| description: OD input port, usually from an AAL block | |
| port@1: | |
| $ref: /schemas/graph.yaml#/properties/port | |
| description: | |
| OD output to the input of the next desired component in the | |
| display pipeline, for example one of the available RDMA or | |
| other blocks. | |
| required: | |
| - port@0 | |
| - port@1 | |
| mediatek,gce-client-reg: | |
| $ref: /schemas/types.yaml#/definitions/phandle-array | |
| description: describes how to locate the GCE client register | |
| items: | |
| - items: | |
| - description: Phandle reference to a Mediatek GCE Mailbox | |
| - description: | |
| GCE subsys id mapping to a client defined in header | |
| include/dt-bindings/gce/<chip>-gce.h. | |
| - description: offset for the GCE register offset | |
| - description: size of the GCE register offset | |
| required: | |
| - compatible | |
| - reg | |
| - clocks | |
| additionalProperties: false | |
| examples: | |
| - | | |
| #include <dt-bindings/clock/mt8173-clk.h> | |
| #include <dt-bindings/gce/mt8173-gce.h> | |
| soc { | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| od@14023000 { | |
| compatible = "mediatek,mt8173-disp-od"; | |
| reg = <0 0x14023000 0 0x1000>; | |
| clocks = <&mmsys CLK_MM_DISP_OD>; | |
| mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; | |
| }; | |
| }; |