| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| %YAML 1.2 | |
| --- | |
| $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml# | |
| $schema: http://devicetree.org/meta-schemas/core.yaml# | |
| title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry | |
| maintainers: | |
| - Conor Dooley <conor.dooley@microchip.com> | |
| description: | | |
| Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of | |
| these blocks contains two PLLs and 2 DLLs & are located in the four corners of | |
| the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at: | |
| https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html | |
| properties: | |
| compatible: | |
| oneOf: | |
| - items: | |
| - const: microchip,pic64gx-ccc | |
| - const: microchip,mpfs-ccc | |
| - const: microchip,mpfs-ccc | |
| reg: | |
| items: | |
| - description: PLL0's control registers | |
| - description: PLL1's control registers | |
| - description: DLL0's control registers | |
| - description: DLL1's control registers | |
| clocks: | |
| description: | |
| The CCC PLL's have two input clocks. It is required that even if the input | |
| clocks are identical that both are provided. | |
| minItems: 2 | |
| items: | |
| - description: PLL0's refclk0 | |
| - description: PLL0's refclk1 | |
| - description: PLL1's refclk0 | |
| - description: PLL1's refclk1 | |
| - description: DLL0's refclk | |
| - description: DLL1's refclk | |
| clock-names: | |
| minItems: 2 | |
| items: | |
| - const: pll0_ref0 | |
| - const: pll0_ref1 | |
| - const: pll1_ref0 | |
| - const: pll1_ref1 | |
| - const: dll0_ref | |
| - const: dll1_ref | |
| '#clock-cells': | |
| const: 1 | |
| description: | | |
| The clock consumer should specify the desired clock by having the clock | |
| ID in its "clocks" phandle cell. | |
| See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of | |
| PolarFire clock IDs. | |
| required: | |
| - compatible | |
| - reg | |
| - clocks | |
| - clock-names | |
| - '#clock-cells' | |
| additionalProperties: false | |
| examples: | |
| - | | |
| clock-controller@38100000 { | |
| compatible = "microchip,mpfs-ccc"; | |
| reg = <0x38010000 0x1000>, <0x38020000 0x1000>, | |
| <0x39010000 0x1000>, <0x39020000 0x1000>; | |
| #clock-cells = <1>; | |
| clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, | |
| <&refclk_ccc>, <&refclk_ccc>; | |
| clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", | |
| "dll0_ref", "dll1_ref"; | |
| }; |