| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| %YAML 1.2 | |
| --- | |
| $id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml# | |
| $schema: http://devicetree.org/meta-schemas/core.yaml# | |
| title: Google GS101 SoC clock controller | |
| maintainers: | |
| - Peter Griffin <peter.griffin@linaro.org> | |
| description: | | |
| Google GS101 clock controller is comprised of several CMU units, generating | |
| clocks for different domains. Those CMU units are modeled as separate device | |
| tree nodes, and might depend on each other. The root clock in that clock tree | |
| is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate | |
| clock in dts. | |
| CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and | |
| dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. | |
| Each clock is assigned an identifier and client nodes can use this identifier | |
| to specify the clock which they consume. All clocks available for usage | |
| in clock consumer nodes are defined as preprocessor macros in | |
| 'dt-bindings/clock/gs101.h' header. | |
| properties: | |
| compatible: | |
| enum: | |
| - google,gs101-cmu-top | |
| - google,gs101-cmu-apm | |
| - google,gs101-cmu-dpu | |
| - google,gs101-cmu-hsi0 | |
| - google,gs101-cmu-hsi2 | |
| - google,gs101-cmu-misc | |
| - google,gs101-cmu-peric0 | |
| - google,gs101-cmu-peric1 | |
| clocks: | |
| minItems: 1 | |
| maxItems: 5 | |
| clock-names: | |
| minItems: 1 | |
| maxItems: 5 | |
| "#clock-cells": | |
| const: 1 | |
| power-domains: | |
| maxItems: 1 | |
| reg: | |
| maxItems: 1 | |
| samsung,sysreg: | |
| $ref: /schemas/types.yaml#/definitions/phandle | |
| description: | |
| Phandle to system registers interface. | |
| required: | |
| - compatible | |
| - "#clock-cells" | |
| - clocks | |
| - clock-names | |
| - reg | |
| allOf: | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - google,gs101-cmu-top | |
| - google,gs101-cmu-apm | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: External reference clock (24.576 MHz) | |
| clock-names: | |
| items: | |
| - const: oscclk | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| const: google,gs101-cmu-dpu | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: External reference clock (24.576 MHz) | |
| - description: DPU bus clock (from CMU_TOP) | |
| clock-names: | |
| items: | |
| - const: oscclk | |
| - const: bus | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| const: google,gs101-cmu-hsi0 | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: External reference clock (24.576 MHz) | |
| - description: HSI0 bus clock (from CMU_TOP) | |
| - description: DPGTC (from CMU_TOP) | |
| - description: USB DRD controller clock (from CMU_TOP) | |
| - description: USB Display Port debug clock (from CMU_TOP) | |
| clock-names: | |
| items: | |
| - const: oscclk | |
| - const: bus | |
| - const: dpgtc | |
| - const: usb31drd | |
| - const: usbdpdbg | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - google,gs101-cmu-hsi2 | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: External reference clock (24.576 MHz) | |
| - description: High Speed Interface bus clock (from CMU_TOP) | |
| - description: High Speed Interface pcie clock (from CMU_TOP) | |
| - description: High Speed Interface ufs clock (from CMU_TOP) | |
| - description: High Speed Interface mmc clock (from CMU_TOP) | |
| clock-names: | |
| items: | |
| - const: oscclk | |
| - const: bus | |
| - const: pcie | |
| - const: ufs | |
| - const: mmc | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| const: google,gs101-cmu-misc | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: Misc bus clock (from CMU_TOP) | |
| - description: Misc sss clock (from CMU_TOP) | |
| clock-names: | |
| items: | |
| - const: bus | |
| - const: sss | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - google,gs101-cmu-peric0 | |
| - google,gs101-cmu-peric1 | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: External reference clock (24.576 MHz) | |
| - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP) | |
| - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP) | |
| clock-names: | |
| items: | |
| - const: oscclk | |
| - const: bus | |
| - const: ip | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| const: google,gs101-cmu-top | |
| then: | |
| properties: | |
| samsung,sysreg: false | |
| else: | |
| required: | |
| - samsung,sysreg | |
| additionalProperties: false | |
| examples: | |
| # Clock controller node for CMU_TOP | |
| - | | |
| #include <dt-bindings/clock/google,gs101.h> | |
| cmu_top: clock-controller@1e080000 { | |
| compatible = "google,gs101-cmu-top"; | |
| reg = <0x1e080000 0x10000>; | |
| #clock-cells = <1>; | |
| clocks = <&ext_24_5m>; | |
| clock-names = "oscclk"; | |
| }; | |
| ... |