| // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
| /* |
| * Samsung Exynos 990 SoC device tree source |
| * |
| * Copyright (c) 2024, Igor Belwon <igor.belwon@mentallysanemainliners.org> |
| */ |
| |
| #include <dt-bindings/clock/samsung,exynos990.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| compatible = "samsung,exynos990"; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| |
| interrupt-parent = <&gic>; |
| |
| aliases { |
| pinctrl0 = &pinctrl_alive; |
| pinctrl1 = &pinctrl_cmgp; |
| pinctrl2 = &pinctrl_hsi1; |
| pinctrl3 = &pinctrl_hsi2; |
| pinctrl4 = &pinctrl_peric0; |
| pinctrl5 = &pinctrl_peric1; |
| pinctrl6 = &pinctrl_vts; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&cpu4>; |
| }; |
| |
| core1 { |
| cpu = <&cpu5>; |
| }; |
| }; |
| |
| cluster2 { |
| core0 { |
| cpu = <&cpu6>; |
| }; |
| |
| core1 { |
| cpu = <&cpu7>; |
| }; |
| }; |
| }; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x1>; |
| enable-method = "psci"; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x2>; |
| enable-method = "psci"; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x3>; |
| enable-method = "psci"; |
| }; |
| |
| cpu4: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a76"; |
| reg = <0x4>; |
| enable-method = "psci"; |
| }; |
| |
| cpu5: cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a76"; |
| reg = <0x5>; |
| enable-method = "psci"; |
| }; |
| |
| cpu6: cpu@200 { |
| device_type = "cpu"; |
| compatible = "samsung,mongoose-m5"; |
| reg = <0x6>; |
| enable-method = "psci"; |
| }; |
| |
| cpu7: cpu@201 { |
| device_type = "cpu"; |
| compatible = "samsung,mongoose-m5"; |
| reg = <0x7>; |
| enable-method = "psci"; |
| }; |
| }; |
| |
| oscclk: clock-osc { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-output-names = "oscclk"; |
| }; |
| |
| pmu-a55 { |
| compatible = "arm,cortex-a55-pmu"; |
| interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; |
| |
| interrupt-affinity = <&cpu0>, |
| <&cpu1>, |
| <&cpu2>, |
| <&cpu3>; |
| }; |
| |
| pmu-a76 { |
| compatible = "arm,cortex-a76-pmu"; |
| interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| |
| interrupt-affinity = <&cpu4>, |
| <&cpu5>; |
| }; |
| |
| pmu-mongoose-m5 { |
| compatible = "samsung,mongoose-pmu"; |
| interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; |
| |
| interrupt-affinity = <&cpu6>, |
| <&cpu7>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "hvc"; |
| }; |
| |
| soc: soc@0 { |
| compatible = "simple-bus"; |
| ranges = <0x0 0x0 0x0 0x20000000>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| chipid@10000000 { |
| compatible = "samsung,exynos990-chipid", |
| "samsung,exynos850-chipid"; |
| reg = <0x10000000 0x100>; |
| }; |
| |
| cmu_peris: clock-controller@10020000 { |
| compatible = "samsung,exynos990-cmu-peris"; |
| reg = <0x10020000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, |
| <&cmu_top CLK_DOUT_CMU_PERIS_BUS>; |
| clock-names = "oscclk", "bus"; |
| }; |
| |
| timer@10040000 { |
| compatible = "samsung,exynos990-mct", |
| "samsung,exynos4210-mct"; |
| reg = <0x10040000 0x800>; |
| clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>; |
| clock-names = "fin_pll", "mct"; |
| interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| watchdog_cl0: watchdog@10050000 { |
| compatible = "samsung,exynos990-wdt"; |
| reg = <0x10050000 0x100>; |
| interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK>, |
| <&oscclk>; |
| clock-names = "watchdog", |
| "watchdog_src"; |
| samsung,syscon-phandle = <&pmu_system_controller>; |
| samsung,cluster-index = <0>; |
| }; |
| |
| watchdog_cl2: watchdog@10060000 { |
| compatible = "samsung,exynos990-wdt"; |
| reg = <0x10060000 0x100>; |
| interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK>, |
| <&oscclk>; |
| clock-names = "watchdog", |
| "watchdog_src"; |
| samsung,syscon-phandle = <&pmu_system_controller>; |
| samsung,cluster-index = <2>; |
| }; |
| |
| gic: interrupt-controller@10101000 { |
| compatible = "arm,gic-400"; |
| reg = <0x10101000 0x1000>, |
| <0x10102000 0x1000>, |
| <0x10104000 0x2000>, |
| <0x10106000 0x2000>; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | |
| IRQ_TYPE_LEVEL_HIGH)>; |
| #address-cells = <0>; |
| #size-cells = <1>; |
| }; |
| |
| cmu_peric0: clock-controller@10400000 { |
| compatible = "samsung,exynos990-cmu-peric0"; |
| reg = <0x10400000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, |
| <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, |
| <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; |
| clock-names = "oscclk", "bus", "ip"; |
| }; |
| |
| pinctrl_peric0: pinctrl@10430000 { |
| compatible = "samsung,exynos990-pinctrl"; |
| reg = <0x10430000 0x1000>; |
| interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| cmu_peric1: clock-controller@10700000 { |
| compatible = "samsung,exynos990-cmu-peric1"; |
| reg = <0x10700000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, |
| <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, |
| <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; |
| clock-names = "oscclk", "bus", "ip"; |
| }; |
| |
| pinctrl_peric1: pinctrl@10730000 { |
| compatible = "samsung,exynos990-pinctrl"; |
| reg = <0x10730000 0x1000>; |
| interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| cmu_hsi0: clock-controller@10a00000 { |
| compatible = "samsung,exynos990-cmu-hsi0"; |
| reg = <0x10a00000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, |
| <&cmu_top CLK_DOUT_CMU_HSI0_BUS>, |
| <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>, |
| <&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>, |
| <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>; |
| clock-names = "oscclk", |
| "bus", |
| "usb31drd", |
| "usbdp_debug", |
| "dpgtc"; |
| }; |
| |
| usbdrd_phy: phy@10c00000 { |
| compatible = "samsung,exynos990-usbdrd-phy"; |
| reg = <0x10c00000 0x100>; |
| clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, |
| <&oscclk>; |
| clock-names = "phy", "ref"; |
| samsung,pmu-syscon = <&pmu_system_controller>; |
| #phy-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| usbdrd: usb@10e00000 { |
| compatible = "samsung,exynos990-dwusb3", |
| "samsung,exynos850-dwusb3"; |
| ranges = <0x0 0x10e00000 0x10000>; |
| clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, |
| <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40>; |
| clock-names = "bus_early", "ref"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| status = "disabled"; |
| |
| usbdrd_dwc3: usb@0 { |
| compatible = "snps,dwc3"; |
| reg = <0x0 0x10000>; |
| interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&usbdrd_phy 0>; |
| phy-names = "usb2-phy"; |
| }; |
| }; |
| |
| pinctrl_hsi1: pinctrl@13040000 { |
| compatible = "samsung,exynos990-pinctrl"; |
| reg = <0x13040000 0x1000>; |
| interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pinctrl_hsi2: pinctrl@13c30000 { |
| compatible = "samsung,exynos990-pinctrl"; |
| reg = <0x13c30000 0x1000>; |
| interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pinctrl_vts: pinctrl@15580000 { |
| compatible = "samsung,exynos990-pinctrl"; |
| reg = <0x15580000 0x1000>; |
| }; |
| |
| pinctrl_alive: pinctrl@15850000 { |
| compatible = "samsung,exynos990-pinctrl"; |
| reg = <0x15850000 0x1000>; |
| |
| wakeup-interrupt-controller { |
| compatible = "samsung,exynos990-wakeup-eint", |
| "samsung,exynos850-wakeup-eint", |
| "samsung,exynos7-wakeup-eint"; |
| }; |
| }; |
| |
| pmu_system_controller: system-controller@15860000 { |
| compatible = "samsung,exynos990-pmu", |
| "samsung,exynos7-pmu", "syscon"; |
| reg = <0x15860000 0x10000>; |
| |
| reboot: syscon-reboot { |
| compatible = "syscon-reboot"; |
| regmap = <&pmu_system_controller>; |
| offset = <0x3a00>; /* SWRESET */ |
| mask = <0x2>; /* SWRESET_TRIGGER */ |
| value = <0x2>; |
| }; |
| }; |
| |
| pinctrl_cmgp: pinctrl@15c30000 { |
| compatible = "samsung,exynos990-pinctrl"; |
| reg = <0x15c30000 0x1000>; |
| }; |
| |
| cmu_top: clock-controller@1a330000 { |
| compatible = "samsung,exynos990-cmu-top"; |
| reg = <0x1a330000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>; |
| clock-names = "oscclk"; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
| |
| /* |
| * Non-updatable, broken stock Samsung bootloader does not |
| * configure CNTFRQ_EL0 |
| */ |
| clock-frequency = <26000000>; |
| }; |
| }; |
| |
| #include "exynos990-pinctrl.dtsi" |
