| // SPDX-License-Identifier: BSD-3-Clause |
| /* |
| * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. |
| */ |
| |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/clock/qcom,sm8750-gcc.h> |
| #include <dt-bindings/clock/qcom,sm8750-tcsr.h> |
| #include <dt-bindings/dma/qcom-gpi.h> |
| #include <dt-bindings/interconnect/qcom,icc.h> |
| #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/qcom,rpmhpd.h> |
| #include <dt-bindings/power/qcom-rpmpd.h> |
| #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
| |
| / { |
| interrupt-parent = <&intc>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "qcom,oryon"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_0>; |
| power-domains = <&cpu_pd0>; |
| power-domain-names = "psci"; |
| |
| l2_0: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| }; |
| }; |
| |
| cpu1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "qcom,oryon"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_0>; |
| power-domains = <&cpu_pd1>; |
| power-domain-names = "psci"; |
| }; |
| |
| cpu2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "qcom,oryon"; |
| reg = <0x0 0x200>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_0>; |
| power-domains = <&cpu_pd2>; |
| power-domain-names = "psci"; |
| }; |
| |
| cpu3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "qcom,oryon"; |
| reg = <0x0 0x300>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_0>; |
| power-domains = <&cpu_pd3>; |
| power-domain-names = "psci"; |
| }; |
| |
| cpu4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "qcom,oryon"; |
| reg = <0x0 0x400>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_0>; |
| power-domains = <&cpu_pd4>; |
| power-domain-names = "psci"; |
| }; |
| |
| cpu5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "qcom,oryon"; |
| reg = <0x0 0x500>; |
| enable-method = "psci"; |
| next-level-cache = <&l2_0>; |
| power-domains = <&cpu_pd5>; |
| power-domain-names = "psci"; |
| }; |
| |
| cpu6: cpu@10000 { |
| device_type = "cpu"; |
| compatible = "qcom,oryon"; |
| reg = <0x0 0x10000>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_1>; |
| power-domains = <&cpu_pd6>; |
| power-domain-names = "psci"; |
| |
| L2_1: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| }; |
| }; |
| |
| cpu7: cpu@10100 { |
| device_type = "cpu"; |
| compatible = "qcom,oryon"; |
| reg = <0x0 0x10100>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_1>; |
| power-domains = <&cpu_pd7>; |
| power-domain-names = "psci"; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| |
| core4 { |
| cpu = <&cpu4>; |
| }; |
| |
| core5 { |
| cpu = <&cpu5>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&cpu6>; |
| }; |
| |
| core1 { |
| cpu = <&cpu7>; |
| }; |
| }; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| cluster0_c4: cpu-sleep-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "ret"; |
| arm,psci-suspend-param = <0x00000004>; |
| entry-latency-us = <93>; |
| exit-latency-us = <129>; |
| min-residency-us = <560>; |
| }; |
| |
| cluster1_c4: cpu-sleep-1 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "ret"; |
| arm,psci-suspend-param = <0x00000004>; |
| entry-latency-us = <172>; |
| exit-latency-us = <130>; |
| min-residency-us = <686>; |
| }; |
| |
| }; |
| |
| domain-idle-states { |
| cluster_cl5: cluster-sleep-0 { |
| compatible = "domain-idle-state"; |
| arm,psci-suspend-param = <0x01000054>; |
| entry-latency-us = <2150>; |
| exit-latency-us = <1983>; |
| min-residency-us = <9144>; |
| }; |
| |
| domain_ss3: domain-sleep-0 { |
| compatible = "domain-idle-state"; |
| arm,psci-suspend-param = <0x0200c354>; |
| entry-latency-us = <2800>; |
| exit-latency-us = <4400>; |
| min-residency-us = <10150>; |
| }; |
| }; |
| }; |
| |
| firmware { |
| scm: scm { |
| compatible = "qcom,scm-sm8750", "qcom,scm"; |
| interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| }; |
| }; |
| |
| clk_virt: interconnect-0 { |
| compatible = "qcom,sm8750-clk-virt"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| mc_virt: interconnect-1 { |
| compatible = "qcom,sm8750-mc-virt"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| memory@a0000000 { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the size */ |
| reg = <0x0 0xa0000000 0x0 0x0>; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| |
| cpu_pd0: power-domain-cpu0 { |
| #power-domain-cells = <0>; |
| power-domains = <&cluster_pd>; |
| domain-idle-states = <&cluster0_c4>; |
| }; |
| |
| cpu_pd1: power-domain-cpu1 { |
| #power-domain-cells = <0>; |
| power-domains = <&cluster_pd>; |
| domain-idle-states = <&cluster0_c4>; |
| }; |
| |
| cpu_pd2: power-domain-cpu2 { |
| #power-domain-cells = <0>; |
| power-domains = <&cluster_pd>; |
| domain-idle-states = <&cluster0_c4>; |
| }; |
| |
| cpu_pd3: power-domain-cpu3 { |
| #power-domain-cells = <0>; |
| power-domains = <&cluster_pd>; |
| domain-idle-states = <&cluster0_c4>; |
| }; |
| |
| cpu_pd4: power-domain-cpu4 { |
| #power-domain-cells = <0>; |
| power-domains = <&cluster_pd>; |
| domain-idle-states = <&cluster0_c4>; |
| }; |
| |
| cpu_pd5: power-domain-cpu5 { |
| #power-domain-cells = <0>; |
| power-domains = <&cluster_pd>; |
| domain-idle-states = <&cluster0_c4>; |
| }; |
| |
| cpu_pd6: power-domain-cpu6 { |
| #power-domain-cells = <0>; |
| power-domains = <&cluster_pd>; |
| domain-idle-states = <&cluster1_c4>; |
| }; |
| |
| cpu_pd7: power-domain-cpu7 { |
| #power-domain-cells = <0>; |
| power-domains = <&cluster_pd>; |
| domain-idle-states = <&cluster1_c4>; |
| }; |
| |
| cluster_pd: power-domain-cluster { |
| #power-domain-cells = <0>; |
| domain-idle-states = <&cluster_cl5>; |
| power-domains = <&system_pd>; |
| }; |
| |
| system_pd: power-domain-system { |
| #power-domain-cells = <0>; |
| domain-idle-states = <&domain_ss3>; |
| }; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gunyah_hyp_mem: gunyah-hyp@80000000 { |
| reg = <0x0 0x80000000 0x0 0xe00000>; |
| no-map; |
| }; |
| |
| cpusys_vm_mem: cpusys-vm-mem@80e00000 { |
| reg = <0x0 0x80e00000 0x0 0x40000>; |
| no-map; |
| }; |
| |
| cpucp_mem: cpucp@81200000 { |
| reg = <0x0 0x81200000 0x0 0x200000>; |
| no-map; |
| }; |
| |
| xbl_dtlog_mem: xbl-dtlog@81a00000 { |
| reg = <0x0 0x81a00000 0x0 0x40000>; |
| no-map; |
| }; |
| |
| aop_image_mem: aop-image@81c00000 { |
| reg = <0x0 0x81c00000 0x0 0x60000>; |
| no-map; |
| }; |
| |
| aop_cmd_db_mem: aop-cmd-db@81c60000 { |
| compatible = "qcom,cmd-db"; |
| reg = <0x0 0x81c60000 0x0 0x20000>; |
| no-map; |
| }; |
| |
| /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ |
| aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { |
| reg = <0x0 0x81c80000 0x0 0x74000>; |
| no-map; |
| }; |
| |
| /* Secdata region can be reused by apps */ |
| |
| smem_mem: smem@81d00000 { |
| compatible = "qcom,smem"; |
| reg = <0x0 0x81d00000 0x0 0x200000>; |
| hwlocks = <&tcsr_mutex 3>; |
| no-map; |
| }; |
| |
| pdp_ns_shared_mem: pdp-ns-shared@81f00000 { |
| reg = <0x0 0x81f00000 0x0 0x100000>; |
| no-map; |
| }; |
| |
| cpucp_scandump_mem: cpucp-scandump@82000000 { |
| reg = <0x0 0x82000000 0x0 0x380000>; |
| no-map; |
| }; |
| |
| adsp_mhi_mem: adsp-mhi@82380000 { |
| reg = <0x0 0x82380000 0x0 0x20000>; |
| no-map; |
| }; |
| |
| soccp_sdi_mem: soccp-sdi@823a0000 { |
| reg = <0x0 0x823a0000 0x0 0x40000>; |
| no-map; |
| }; |
| |
| pmic_minii_dump_mem: pmic-minii-dump@823e0000 { |
| reg = <0x0 0x823e0000 0x0 0x80000>; |
| no-map; |
| }; |
| |
| pvmfw_mem: pvmfw@824a0000 { |
| reg = <0x0 0x824a0000 0x0 0x100000>; |
| no-map; |
| }; |
| |
| global_sync_mem: global-sync@82600000 { |
| reg = <0x0 0x82600000 0x0 0x100000>; |
| no-map; |
| }; |
| |
| tz_stat_mem: tz-stat@82700000 { |
| reg = <0x0 0x82700000 0x0 0x100000>; |
| no-map; |
| }; |
| |
| qdss_mem: qdss@82800000 { |
| reg = <0x0 0x82800000 0x0 0x2000000>; |
| no-map; |
| }; |
| |
| dsm_partition_1_mem: dsm-partition-1@84a00000 { |
| reg = <0x0 0x84a00000 0x0 0x4900000>; |
| no-map; |
| }; |
| |
| dsm_partition_2_mem: dsm-partition-2@89300000 { |
| reg = <0x0 0x89300000 0x0 0xa80000>; |
| no-map; |
| }; |
| |
| mpss_mem: mpss@8ba00000 { |
| reg = <0x0 0x8ba00000 0x0 0xf600000>; |
| no-map; |
| }; |
| |
| q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { |
| reg = <0x0 0x9b000000 0x0 0x80000>; |
| no-map; |
| }; |
| |
| ipa_fw_mem: ipa-fw@9b080000 { |
| reg = <0x0 0x9b080000 0x0 0x10000>; |
| no-map; |
| }; |
| |
| ipa_gsi_mem: ipa-gsi@9b090000 { |
| reg = <0x0 0x9b090000 0x0 0xa000>; |
| no-map; |
| }; |
| |
| gpu_micro_code_mem: gpu-micro-code@9b09a000 { |
| reg = <0x0 0x9b09a000 0x0 0x2000>; |
| no-map; |
| }; |
| |
| spss_region_mem: spss@9b0a0000 { |
| reg = <0x0 0x9b0a0000 0x0 0x1e0000>; |
| no-map; |
| }; |
| |
| /* First part of the "SPU secure shared memory" region */ |
| spu_tz_shared_mem: spu-tz-shared@9b280000 { |
| reg = <0x0 0x9b280000 0x0 0x40000>; |
| no-map; |
| }; |
| |
| /* Second part of the "SPU secure shared memory" region */ |
| spu_modem_shared_mem: spu-modem-shared@9b2c0000 { |
| reg = <0x0 0x9b2c0000 0x0 0x40000>; |
| no-map; |
| }; |
| |
| camera_mem: camera@9b300000 { |
| reg = <0x0 0x9b300000 0x0 0x800000>; |
| no-map; |
| }; |
| |
| camera_2_mem: camera-2@9bb00000 { |
| reg = <0x0 0x9bb00000 0x0 0x800000>; |
| no-map; |
| }; |
| |
| video_mem: video@9c300000 { |
| reg = <0x0 0x9c300000 0x0 0x800000>; |
| no-map; |
| }; |
| |
| cvp_mem: cvp@9cb00000 { |
| reg = <0x0 0x9cb00000 0x0 0x700000>; |
| no-map; |
| }; |
| |
| cdsp_mem: cdsp@9d200000 { |
| reg = <0x0 0x9d200000 0x0 0x1900000>; |
| no-map; |
| }; |
| |
| q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 { |
| reg = <0x0 0x9eb00000 0x0 0x80000>; |
| no-map; |
| }; |
| |
| soccp_mem: soccp@9ec00000 { |
| reg = <0x0 0x9ec00000 0x0 0x180000>; |
| no-map; |
| }; |
| |
| q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 { |
| reg = <0x0 0x9ed80000 0x0 0x80000>; |
| no-map; |
| }; |
| |
| adspslpi_mem: adspslpi@9ee00000 { |
| reg = <0x0 0x9ee00000 0x0 0x3a80000>; |
| no-map; |
| }; |
| |
| xbl_ramdump_mem: xbl-ramdump@b8000000 { |
| reg = <0x0 0xb8000000 0x0 0x1c0000>; |
| no-map; |
| }; |
| |
| hwfence_shbuf: hwfence-shbuf@d4e23000 { |
| no-map; |
| reg = <0x0 0xd4e23000 0x0 0x2dd000>; |
| }; |
| |
| /* Merged tz_reserved, xbl_sc, and qtee regions */ |
| tz_merged_mem: tz-merged@d8000000 { |
| reg = <0x0 0xd8000000 0x0 0x600000>; |
| no-map; |
| }; |
| |
| trust_ui_vm_mem: trust-ui-vm@f3800000 { |
| reg = <0x0 0xf3800000 0x0 0x4400000>; |
| no-map; |
| }; |
| |
| oem_vm_mem: oem-vm@f7c00000 { |
| reg = <0x0 0xf7c00000 0x0 0x4c00000>; |
| no-map; |
| }; |
| |
| llcc_lpi_mem: llcc-lpi@ff800000 { |
| reg = <0x0 0xff800000 0x0 0x800000>; |
| no-map; |
| }; |
| }; |
| |
| soc: soc@0 { |
| compatible = "simple-bus"; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| dma-ranges = <0 0 0 0 0x10 0>; |
| ranges = <0 0 0 0 0x10 0>; |
| |
| gcc: clock-controller@100000 { |
| compatible = "qcom,sm8750-gcc"; |
| reg = <0x0 0x00100000 0x0 0x1f4200>; |
| |
| clocks = <&bi_tcxo_div2>, |
| <0>, |
| <&sleep_clk>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>; |
| |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| gpi_dma2: dma-controller@800000 { |
| compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; |
| reg = <0x0 0x00800000 0x0 0x60000>; |
| |
| interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; |
| |
| dma-channels = <12>; |
| dma-channel-mask = <0x1e>; |
| #dma-cells = <3>; |
| |
| iommus = <&apps_smmu 0x436 0x0>; |
| |
| status = "disabled"; |
| }; |
| |
| qupv3_2: geniqup@8c0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0x0 0x008c0000 0x0 0x2000>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| clock-names = "m-ahb", |
| "s-ahb"; |
| |
| iommus = <&apps_smmu 0x423 0x0>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| status = "disabled"; |
| |
| i2c8: i2c@880000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x00880000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 0 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c8_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi8: spi@880000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x00880000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 0 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c9: i2c@884000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x00884000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 1 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c9_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi9: spi@884000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x00884000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 1 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c10: i2c@888000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x00888000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 2 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c10_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi10: spi@888000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x00888000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 2 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c11: i2c@88c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x0088c000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 3 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c11_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi11: spi@88c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x0088c000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 3 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c12: i2c@890000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x00890000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 4 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c12_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi12: spi@890000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x00890000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 4 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c13: i2c@894000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x00894000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 5 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c13_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi13: spi@894000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x00894000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 5 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| uart14: serial@898000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0x0 0x00898000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config"; |
| |
| pinctrl-0 = <&qup_uart14_default>; |
| pinctrl-names = "default"; |
| |
| status = "disabled"; |
| }; |
| |
| i2c15: i2c@89c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x0089c000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, |
| <&gpi_dma2 1 7 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c15_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi15: spi@89c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x0089c000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, |
| <&gpi_dma2 1 7 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| }; |
| |
| i2c_master_hub_0: geniqup@9c0000 { |
| compatible = "qcom,geni-se-i2c-master-hub"; |
| reg = <0x0 0x009c0000 0x0 0x2000>; |
| |
| clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; |
| clock-names = "s-ahb"; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| status = "disabled"; |
| |
| i2c_hub_0: i2c@980000 { |
| compatible = "qcom,geni-i2c-master-hub"; |
| reg = <0x0 0x00980000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, |
| <&gcc GCC_QUPV3_I2C_CORE_CLK>; |
| clock-names = "se", |
| "core"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config"; |
| |
| pinctrl-0 = <&hub_i2c0_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c_hub_1: i2c@984000 { |
| compatible = "qcom,geni-i2c-master-hub"; |
| reg = <0x0 0x00984000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, |
| <&gcc GCC_QUPV3_I2C_CORE_CLK>; |
| clock-names = "se", |
| "core"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config"; |
| |
| pinctrl-0 = <&hub_i2c1_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c_hub_2: i2c@988000 { |
| compatible = "qcom,geni-i2c-master-hub"; |
| reg = <0x0 0x00988000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, |
| <&gcc GCC_QUPV3_I2C_CORE_CLK>; |
| clock-names = "se", |
| "core"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config"; |
| |
| pinctrl-0 = <&hub_i2c2_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c_hub_3: i2c@98c000 { |
| compatible = "qcom,geni-i2c-master-hub"; |
| reg = <0x0 0x0098c000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, |
| <&gcc GCC_QUPV3_I2C_CORE_CLK>; |
| clock-names = "se", |
| "core"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config"; |
| |
| pinctrl-0 = <&hub_i2c3_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c_hub_4: i2c@990000 { |
| compatible = "qcom,geni-i2c-master-hub"; |
| reg = <0x0 0x00990000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, |
| <&gcc GCC_QUPV3_I2C_CORE_CLK>; |
| clock-names = "se", |
| "core"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config"; |
| |
| pinctrl-0 = <&hub_i2c4_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c_hub_5: i2c@994000 { |
| compatible = "qcom,geni-i2c-master-hub"; |
| reg = <0x0 0x00994000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, |
| <&gcc GCC_QUPV3_I2C_CORE_CLK>; |
| clock-names = "se", |
| "core"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config"; |
| |
| pinctrl-0 = <&hub_i2c5_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c_hub_6: i2c@998000 { |
| compatible = "qcom,geni-i2c-master-hub"; |
| reg = <0x0 0x00998000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, |
| <&gcc GCC_QUPV3_I2C_CORE_CLK>; |
| clock-names = "se", |
| "core"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config"; |
| |
| pinctrl-0 = <&hub_i2c6_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c_hub_7: i2c@99c000 { |
| compatible = "qcom,geni-i2c-master-hub"; |
| reg = <0x0 0x0099c000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, |
| <&gcc GCC_QUPV3_I2C_CORE_CLK>; |
| clock-names = "se", |
| "core"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config"; |
| |
| pinctrl-0 = <&hub_i2c7_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c_hub_8: i2c@9a0000 { |
| compatible = "qcom,geni-i2c-master-hub"; |
| reg = <0x0 0x009a0000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, |
| <&gcc GCC_QUPV3_I2C_CORE_CLK>; |
| clock-names = "se", |
| "core"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config"; |
| |
| pinctrl-0 = <&hub_i2c8_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c_hub_9: i2c@9a4000 { |
| compatible = "qcom,geni-i2c-master-hub"; |
| reg = <0x0 0x009a4000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, |
| <&gcc GCC_QUPV3_I2C_CORE_CLK>; |
| clock-names = "se", |
| "core"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config"; |
| |
| pinctrl-0 = <&hub_i2c9_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| }; |
| |
| gpi_dma1: dma-controller@a00000 { |
| compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; |
| reg = <0x0 0x00a00000 0x0 0x60000>; |
| |
| interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; |
| |
| dma-channels = <12>; |
| dma-channel-mask = <0x1e>; |
| #dma-cells = <3>; |
| |
| iommus = <&apps_smmu 0xb6 0x0>; |
| |
| status = "disabled"; |
| }; |
| |
| qupv3_1: geniqup@ac0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0x0 0x00ac0000 0x0 0x2000>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| clock-names = "m-ahb", |
| "s-ahb"; |
| |
| iommus = <&apps_smmu 0xa3 0x0>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| status = "disabled"; |
| |
| i2c0: i2c@a80000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x00a80000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 0 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c0_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi0: spi@a80000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x00a80000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 0 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@a84000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x00a84000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 1 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c1_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi1: spi@a84000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x00a84000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 1 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@a88000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x00a88000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 2 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c2_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi2: spi@a88000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x00a88000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 2 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@a8c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x00a8c000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 3 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c3_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi3: spi@a8c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x00a8c000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 3 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@a90000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x00a90000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 4 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c4_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi4: spi@a90000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x00a90000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 4 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@a94000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x00a94000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 5 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c5_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi5: spi@a94000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x00a94000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 5 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@a98000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0x0 0x00a98000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 6 QCOM_GPI_I2C>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_i2c6_data_clk>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| spi6: spi@a98000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0x0 0x00a98000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, |
| <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config", |
| "qup-memory"; |
| |
| dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, |
| <&gpi_dma1 1 6 QCOM_GPI_SPI>; |
| dma-names = "tx", |
| "rx"; |
| |
| pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; |
| pinctrl-names = "default"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| uart7: serial@a9c000 { |
| compatible = "qcom,geni-debug-uart"; |
| reg = <0x0 0x00a9c000 0x0 0x4000>; |
| |
| interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
| clock-names = "se"; |
| |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS |
| &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "qup-core", |
| "qup-config"; |
| |
| |
| pinctrl-0 = <&qup_uart7_default>; |
| pinctrl-names = "default"; |
| |
| status = "disabled"; |
| }; |
| }; |
| |
| cnoc_main: interconnect@1500000 { |
| compatible = "qcom,sm8750-cnoc-main"; |
| reg = <0x0 0x01500000 0x0 0x16080>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| #interconnect-cells = <2>; |
| }; |
| |
| config_noc: interconnect@1600000 { |
| compatible = "qcom,sm8750-config-noc"; |
| reg = <0x0 0x01600000 0x0 0x6200>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| #interconnect-cells = <2>; |
| }; |
| |
| system_noc: interconnect@1680000 { |
| compatible = "qcom,sm8750-system-noc"; |
| reg = <0x0 0x01680000 0x0 0x1d080>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| #interconnect-cells = <2>; |
| }; |
| |
| pcie_noc: interconnect@16c0000 { |
| compatible = "qcom,sm8750-pcie-anoc"; |
| reg = <0x0 0x016c0000 0x0 0x11400>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| #interconnect-cells = <2>; |
| clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, |
| <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; |
| |
| }; |
| |
| aggre1_noc: interconnect@16e0000 { |
| compatible = "qcom,sm8750-aggre1-noc"; |
| reg = <0x0 0x016e0000 0x0 0x16400>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| #interconnect-cells = <2>; |
| clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, |
| <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; |
| |
| }; |
| |
| aggre2_noc: interconnect@1700000 { |
| compatible = "qcom,sm8750-aggre2-noc"; |
| reg = <0x0 0x01700000 0x0 0x1f400>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| #interconnect-cells = <2>; |
| clocks = <&rpmhcc RPMH_IPA_CLK>; |
| }; |
| |
| mmss_noc: interconnect@1780000 { |
| compatible = "qcom,sm8750-mmss-noc"; |
| reg = <0x0 0x01780000 0x0 0x5b800>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| #interconnect-cells = <2>; |
| }; |
| |
| tcsr_mutex: hwlock@1f40000 { |
| compatible = "qcom,tcsr-mutex"; |
| reg = <0x0 0x01f40000 0x0 0x20000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| lpass_ag_noc: interconnect@7e40000 { |
| compatible = "qcom,sm8750-lpass-ag-noc"; |
| reg = <0x0 0x07e40000 0x0 0xe080>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| #interconnect-cells = <2>; |
| }; |
| |
| lpass_lpiaon_noc: interconnect@7400000 { |
| compatible = "qcom,sm8750-lpass-lpiaon-noc"; |
| reg = <0x0 0x07400000 0x0 0x19080>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| #interconnect-cells = <2>; |
| }; |
| |
| lpass_lpicx_noc: interconnect@7420000 { |
| compatible = "qcom,sm8750-lpass-lpicx-noc"; |
| reg = <0x0 0x07420000 0x0 0x44080>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| #interconnect-cells = <2>; |
| }; |
| |
| pdc: interrupt-controller@b220000 { |
| compatible = "qcom,sm8750-pdc", "qcom,pdc"; |
| reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; |
| |
| qcom,pdc-ranges = <0 745 51>, <51 527 47>, |
| <98 609 32>, <130 717 12>, |
| <142 251 5>, <147 796 16>; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&intc>; |
| interrupt-controller; |
| }; |
| |
| spmi_bus: spmi@c400000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0x0 0x0c400000 0x0 0x3000>, |
| <0x0 0x0c500000 0x0 0x400000>, |
| <0x0 0x0c440000 0x0 0x80000>, |
| <0x0 0x0c4c0000 0x0 0x10000>, |
| <0x0 0x0c42d000 0x0 0x4000>; |
| reg-names = "core", |
| "chnls", |
| "obsrvr", |
| "intr", |
| "cnfg"; |
| |
| interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "periph_irq"; |
| |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| qcom,bus-id = <0>; |
| |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| |
| #address-cells = <2>; |
| #size-cells = <0>; |
| }; |
| |
| tlmm: pinctrl@f100000 { |
| compatible = "qcom,sm8750-tlmm"; |
| reg = <0x0 0x0f100000 0x0 0x102000>; |
| |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| |
| gpio-ranges = <&tlmm 0 0 216>; |
| wakeup-parent = <&pdc>; |
| |
| hub_i2c0_data_clk: hub-i2c0-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio64", "gpio65"; |
| function = "i2chub0_se0"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| hub_i2c1_data_clk: hub-i2c1-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio66", "gpio67"; |
| function = "i2chub0_se1"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| hub_i2c2_data_clk: hub-i2c2-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio68", "gpio69"; |
| function = "i2chub0_se2"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| hub_i2c3_data_clk: hub-i2c3-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio70", "gpio71"; |
| function = "i2chub0_se3"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| hub_i2c4_data_clk: hub-i2c4-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio72", "gpio73"; |
| function = "i2chub0_se4"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| hub_i2c5_data_clk: hub-i2c5-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio74", "gpio75"; |
| function = "i2chub0_se5"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| hub_i2c6_data_clk: hub-i2c6-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio76", "gpio77"; |
| function = "i2chub0_se6"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| hub_i2c7_data_clk: hub-i2c7-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio82", "gpio83"; |
| function = "i2chub0_se7"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| hub_i2c8_data_clk: hub-i2c8-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio206", "gpio207"; |
| function = "i2chub0_se8"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| hub_i2c9_data_clk: hub-i2c9-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio80", "gpio81"; |
| function = "i2chub0_se9"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| pcie0_default_state: pcie0-default-state { |
| perst-pins { |
| pins = "gpio102"; |
| function = "gpio"; |
| drive-strength = <2>; |
| bias-pull-down; |
| }; |
| |
| clkreq-pins { |
| pins = "gpio103"; |
| function = "pcie0_clk_req_n"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| wake-pins { |
| pins = "gpio104"; |
| function = "gpio"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| |
| qup_i2c0_data_clk: qup-i2c0-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio32", "gpio33"; |
| function = "qup1_se0"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c1_data_clk: qup-i2c1-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio36", "gpio37"; |
| function = "qup1_se1"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c2_data_clk: qup-i2c2-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio40", "gpio41"; |
| function = "qup1_se2"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c3_data_clk: qup-i2c3-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio44", "gpio45"; |
| function = "qup1_se3"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c4_data_clk: qup-i2c4-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio48", "gpio49"; |
| function = "qup1_se4"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c5_data_clk: qup-i2c5-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio52", "gpio53"; |
| function = "qup1_se5"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c6_data_clk: qup-i2c6-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio56", "gpio57"; |
| function = "qup1_se6"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c8_data_clk: qup-i2c8-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio0", "gpio1"; |
| function = "qup2_se0"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c9_data_clk: qup-i2c9-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio4", "gpio5"; |
| function = "qup2_se1"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c10_data_clk: qup-i2c10-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio8", "gpio9"; |
| function = "qup2_se2"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c11_data_clk: qup-i2c11-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio12", "gpio13"; |
| function = "qup2_se3"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c12_data_clk: qup-i2c12-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio16", "gpio17"; |
| function = "qup2_se4"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c13_data_clk: qup-i2c13-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio20", "gpio21"; |
| function = "qup2_se5"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_i2c15_data_clk: qup-i2c15-data-clk-state { |
| /* SDA, SCL */ |
| pins = "gpio28", "gpio29"; |
| function = "qup2_se7"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_spi0_cs: qup-spi0-cs-state { |
| pins = "gpio35"; |
| function = "qup1_se0"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi0_data_clk: qup-spi0-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio32", "gpio33", "gpio34"; |
| function = "qup1_se0"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi1_cs: qup-spi1-cs-state { |
| pins = "gpio39"; |
| function = "qup1_se1"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi1_data_clk: qup-spi1-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio36", "gpio37", "gpio38"; |
| function = "qup1_se1"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi2_cs: qup-spi2-cs-state { |
| pins = "gpio43"; |
| function = "qup1_se2"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi2_data_clk: qup-spi2-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio40", "gpio41", "gpio42"; |
| function = "qup1_se2"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi3_cs: qup-spi3-cs-state { |
| pins = "gpio47"; |
| function = "qup1_se3"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi3_data_clk: qup-spi3-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio44", "gpio45", "gpio46"; |
| function = "qup1_se3"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi4_cs: qup-spi4-cs-state { |
| pins = "gpio51"; |
| function = "qup1_se4"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi4_data_clk: qup-spi4-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio48", "gpio49", "gpio50"; |
| function = "qup1_se4"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi5_cs: qup-spi5-cs-state { |
| pins = "gpio55"; |
| function = "qup1_se5"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi5_data_clk: qup-spi5-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio52", "gpio53", "gpio54"; |
| function = "qup1_se5"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi6_cs: qup-spi6-cs-state { |
| pins = "gpio59"; |
| function = "qup1_se6"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi6_data_clk: qup-spi6-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio56", "gpio57", "gpio58"; |
| function = "qup1_se6"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi8_cs: qup-spi8-cs-state { |
| pins = "gpio3"; |
| function = "qup2_se0"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi8_data_clk: qup-spi8-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio0", "gpio1", "gpio2"; |
| function = "qup2_se0"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi9_cs: qup-spi9-cs-state { |
| pins = "gpio7"; |
| function = "qup2_se1"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi9_data_clk: qup-spi9-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio4", "gpio5", "gpio6"; |
| function = "qup2_se1"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi10_cs: qup-spi10-cs-state { |
| pins = "gpio11"; |
| function = "qup2_se2"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi10_data_clk: qup-spi10-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio8", "gpio9", "gpio10"; |
| function = "qup2_se2"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi11_cs: qup-spi11-cs-state { |
| pins = "gpio15"; |
| function = "qup2_se3"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi11_data_clk: qup-spi11-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio12", "gpio13", "gpio14"; |
| function = "qup2_se3"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi12_cs: qup-spi12-cs-state { |
| pins = "gpio19"; |
| function = "qup2_se4"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi12_data_clk: qup-spi12-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio16", "gpio17", "gpio18"; |
| function = "qup2_se4"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi13_cs: qup-spi13-cs-state { |
| pins = "gpio23"; |
| function = "qup2_se5"; |
| drive-strength = <6>; |
| bias-pull-up; |
| }; |
| |
| qup_spi13_data_clk: qup-spi13-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio20", "gpio21", "gpio22"; |
| function = "qup2_se5"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi15_cs: qup-spi15-cs-state { |
| pins = "gpio31"; |
| function = "qup2_se7"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_spi15_data_clk: qup-spi15-data-clk-state { |
| /* MISO, MOSI, CLK */ |
| pins = "gpio28", "gpio29", "gpio30"; |
| function = "qup2_se7"; |
| drive-strength = <6>; |
| bias-disable; |
| }; |
| |
| qup_uart7_default: qup-uart7-default-state { |
| /* TX, RX */ |
| pins = "gpio62", "gpio63"; |
| function = "qup1_se7"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| qup_uart14_default: qup-uart14-default-state { |
| /* TX, RX */ |
| pins = "gpio26", "gpio27"; |
| function = "qup2_se6"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| qup_uart14_cts_rts: qup-uart14-cts-rts-state { |
| /* CTS, RTS */ |
| pins = "gpio24", "gpio25"; |
| function = "qup2_se6"; |
| drive-strength = <2>; |
| bias-pull-down; |
| }; |
| |
| sdc2_sleep: sdc2-sleep-state { |
| clk-pins { |
| pins = "sdc2_clk"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| cmd-pins { |
| pins = "sdc2_cmd"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| data-pins { |
| pins = "sdc2_data"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| |
| sdc2_default: sdc2-default-state { |
| clk-pins { |
| pins = "sdc2_clk"; |
| drive-strength = <16>; |
| bias-disable; |
| }; |
| |
| cmd-pins { |
| pins = "sdc2_cmd"; |
| drive-strength = <10>; |
| bias-pull-up; |
| }; |
| |
| data-pins { |
| pins = "sdc2_data"; |
| drive-strength = <10>; |
| bias-pull-up; |
| }; |
| }; |
| }; |
| |
| tcsrcc: clock-controller@f204008 { |
| compatible = "qcom,sm8750-tcsr", "syscon"; |
| reg = <0x0 0x0f204008 0x0 0x3004>; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| apps_smmu: iommu@15000000 { |
| compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; |
| reg = <0x0 0x15000000 0x0 0x100000>; |
| |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; |
| |
| #iommu-cells = <2>; |
| #global-interrupts = <1>; |
| |
| dma-coherent; |
| }; |
| |
| intc: interrupt-controller@16000000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x0 0x16000000 0x0 0x10000>, |
| <0x0 0x16080000 0x0 0x200000>; |
| |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x40000>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gic_its: msi-controller@16040000 { |
| compatible = "arm,gic-v3-its"; |
| reg = <0x0 0x16040000 0x0 0x20000>; |
| |
| msi-controller; |
| #msi-cells = <1>; |
| }; |
| }; |
| |
| apps_rsc: rsc@16500000 { |
| compatible = "qcom,rpmh-rsc"; |
| reg = <0x0 0x16500000 0x0 0x10000>, |
| <0x0 0x16510000 0x0 0x10000>, |
| <0x0 0x16520000 0x0 0x10000>; |
| reg-names = "drv-0", |
| "drv-1", |
| "drv-2"; |
| |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,tcs-offset = <0xd00>; |
| qcom,drv-id = <2>; |
| qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, |
| <WAKE_TCS 2>, <CONTROL_TCS 0>; |
| |
| label = "apps_rsc"; |
| |
| power-domains = <&system_pd>; |
| |
| apps_bcm_voter: bcm-voter { |
| compatible = "qcom,bcm-voter"; |
| }; |
| |
| rpmhcc: clock-controller { |
| compatible = "qcom,sm8750-rpmh-clk"; |
| |
| clocks = <&xo_board>; |
| clock-names = "xo"; |
| |
| #clock-cells = <1>; |
| }; |
| |
| rpmhpd: power-controller { |
| compatible = "qcom,sm8750-rpmhpd"; |
| |
| operating-points-v2 = <&rpmhpd_opp_table>; |
| |
| #power-domain-cells = <1>; |
| |
| rpmhpd_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| rpmhpd_opp_ret: opp-16 { |
| opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
| }; |
| |
| rpmhpd_opp_min_svs: opp-48 { |
| opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; |
| }; |
| |
| rpmhpd_opp_low_svs_d3: opp-50 { |
| opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; |
| }; |
| |
| rpmhpd_opp_low_svs_d2: opp-52 { |
| opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; |
| }; |
| |
| rpmhpd_opp_low_svs_d1: opp-56 { |
| opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; |
| }; |
| |
| rpmhpd_opp_low_svs_d0: opp-60 { |
| opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; |
| }; |
| |
| rpmhpd_opp_low_svs: opp-64 { |
| opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
| }; |
| |
| rpmhpd_opp_low_svs_l1: opp-80 { |
| opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; |
| }; |
| |
| rpmhpd_opp_svs: opp-128 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
| }; |
| |
| rpmhpd_opp_svs_l0: opp-144 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; |
| }; |
| |
| rpmhpd_opp_svs_l1: opp-192 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| }; |
| |
| rpmhpd_opp_svs_l2: opp-224 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; |
| }; |
| |
| rpmhpd_opp_nom: opp-256 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
| }; |
| |
| rpmhpd_opp_nom_l1: opp-320 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| }; |
| |
| rpmhpd_opp_nom_l2: opp-336 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; |
| }; |
| |
| rpmhpd_opp_turbo: opp-384 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; |
| }; |
| |
| rpmhpd_opp_turbo_l1: opp-416 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; |
| }; |
| |
| rpmhpd_opp_turbo_l2: opp-432 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; |
| }; |
| |
| rpmhpd_opp_turbo_l3: opp-448 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; |
| }; |
| |
| rpmhpd_opp_turbo_l4: opp-452 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; |
| }; |
| |
| rpmhpd_opp_super_turbo_no_cpr: opp-480 { |
| opp-level = |
| <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>; |
| }; |
| }; |
| }; |
| }; |
| |
| timer@16800000 { |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x0 0x16800000 0x0 0x1000>; |
| |
| #address-cells = <2>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0 0x20000000>; |
| |
| frame@16801000 { |
| reg = <0x0 0x16801000 0x1000>, |
| <0x0 0x16802000 0x1000>; |
| |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| |
| frame-number = <0>; |
| }; |
| |
| frame@16803000 { |
| reg = <0x0 0x16803000 0x1000>; |
| |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| |
| frame-number = <1>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@16805000 { |
| reg = <0x0 0x16805000 0x1000>; |
| |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| |
| frame-number = <2>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@16807000 { |
| reg = <0x0 0x16807000 0x1000>; |
| |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| |
| frame-number = <3>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@16809000 { |
| reg = <0x0 0x16809000 0x1000>; |
| |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| |
| frame-number = <4>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@1680b000 { |
| reg = <0x0 0x1680b000 0x1000>; |
| |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| |
| frame-number = <5>; |
| |
| status = "disabled"; |
| }; |
| |
| frame@1680d000 { |
| reg = <0x0 0x1680d000 0x1000>; |
| |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| |
| frame-number = <6>; |
| |
| status = "disabled"; |
| }; |
| }; |
| |
| gem_noc: interconnect@24100000 { |
| compatible = "qcom,sm8750-gem-noc"; |
| reg = <0x0 0x24100000 0x0 0x14b080>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| #interconnect-cells = <2>; |
| }; |
| |
| nsp_noc: interconnect@320c0000 { |
| compatible = "qcom,sm8750-nsp-noc"; |
| reg = <0x0 0x320c0000 0x0 0x13080>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| #interconnect-cells = <2>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| }; |
