| /* SPDX-License-Identifier: GPL-2.0-only */ |
| |
| #ifndef __SOC_MEDIATEK_MT8195_MMSYS_H |
| #define __SOC_MEDIATEK_MT8195_MMSYS_H |
| |
| #define MT8195_VDO0_OVL_MOUT_EN 0xf14 |
| /* |
| * MT8195_VDO0_OVL_MOUT[2:0]: DISP_OVL0 |
| * BIT(0) : DISP_RDMA0 |
| * BIT(1) : DISP_WDMA0 |
| * BIT(2): DISP_OVL1 |
| */ |
| #define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) |
| #define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) |
| #define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) |
| /* |
| * MT8195_VDO0_OVL_MOUT[6:4]: DISP_OVL1 |
| * BIT(0) : DISP_RDMA1 |
| * BIT(1) : DISP_WDMA1 |
| * BIT(2): DISP_OVL0 |
| */ |
| #define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) |
| #define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) |
| #define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) |
| |
| #define MT8195_VDO0_SEL_IN 0xf34 |
| /* |
| * MT8195_VDO0_SEL_IN[1:0]: VPP_MERGE |
| * 0 : DSC_WRAP0_OUT |
| * 1 : DISP_DITHER1 |
| * 2: VDO1_VIRTUAL0 |
| */ |
| #define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT 0 |
| #define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 BIT(0) |
| #define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 BIT(1) |
| /* |
| * MT8195_VDO0_SEL_IN[4:4]: DSC_WRAP0_IN |
| * 0: DISP_DITHER0 |
| * 1: VPP_MERGE |
| */ |
| #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 0 |
| #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE BIT(4) |
| /* |
| * MT8195_VDO0_SEL_IN[5:5]: DSC_WRAP1_IN |
| * 0: DISP_DITHER1 |
| * 1: VPP_MERGE |
| */ |
| #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 0 |
| #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE BIT(5) |
| /* |
| * MT8195_VDO0_SEL_IN[8:8]: SINA_VIRTUAL0 |
| * 0: VPP_MERGE |
| * 1: DSC_WRAP1_OUT |
| */ |
| #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE 0 |
| #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT BIT(8) |
| /* |
| * MT8195_VDO0_SEL_IN[9:9]: SINB_VIRTUAL0 |
| * 0: DSC_WRAP0_OUT |
| */ |
| #define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT 0 |
| /* |
| * MT8195_VDO0_SEL_IN[13:12]: DP_INTF0 |
| * 0 : DSC_WRAP1_OUT |
| * 1 : VPP_MERGE |
| * 2: VDO1_VIRTUAL0 |
| */ |
| #define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT 0 |
| #define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE BIT(12) |
| #define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 BIT(13) |
| /* |
| * MT8195_VDO0_SEL_IN[16:16]: DSI0 |
| * 0 : DSC_WRAP0_OUT |
| * 1 : DISP_DITHER0 |
| */ |
| #define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT 0 |
| #define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 BIT(16) |
| /* |
| * MT8195_VDO0_SEL_IN[17:17]: DSI1 |
| * 0 : DSC_WRAP1_OUT |
| * 1 : VPP_MERGE |
| */ |
| #define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT 0 |
| #define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE BIT(17) |
| /* |
| * MT8195_VDO0_SEL_IN[20:20]: DISP_WDMA1 |
| * 0 : DISP_OVL1 |
| * 1 : VPP_MERGE |
| */ |
| #define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 0 |
| #define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE BIT(20) |
| /* |
| * MT8195_VDO0_SEL_IN[21:21]: DSC_WRAP1_OUT |
| * 0 : DSC_WRAP1_IN |
| * 1 : DITHER1 |
| */ |
| #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0) |
| #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 BIT(21) |
| /* |
| * MT8195_VDO0_SEL_IN[22:22]: DISP_WDMA0 |
| * 0 : DISP_OVL0 |
| */ |
| #define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 0 |
| |
| #define MT8195_VDO0_SEL_OUT 0xf38 |
| /* |
| * MT8195_VDO0_SOUT[0:0]: DISP_DITHER0 |
| * 0 : DSC_WRAP0_IN |
| * 1 : DSI0 |
| */ |
| #define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN 0 |
| #define MT8195_SOUT_DISP_DITHER0_TO_DSI0 BIT(0) |
| /* |
| * MT8195_VDO0_SOUT[1:1]: DISP_DITHER1 |
| * 0 : DSC_WRAP1_IN |
| * 1 : VPP_MERGE |
| * 2 : DSC_WRAP1_OUT |
| */ |
| #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN 0 |
| #define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE BIT(1) |
| #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT BIT(2) |
| /* |
| * MT8195_VDO0_SOUT[4:4]: VDO1_VIRTUAL0 |
| * 0 : VPP_MERGE |
| * 1 : DP_INTF0 |
| */ |
| #define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE 0 |
| #define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 BIT(4) |
| /* |
| * MT8195_VDO0_SOUT[10:8]: VPP_MERGE |
| * 0 : DSI1 |
| * 1 : DP_INTF0 |
| * 2 : SINA_VIRTUAL0 |
| * 3 : DISP_WDMA1 |
| * 4 : DSC_WRAP0_IN |
| */ |
| #define MT8195_SOUT_VPP_MERGE_TO_DSI1 0 |
| #define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 BIT(8) |
| #define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 BIT(9) |
| #define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (BIT(9) | BIT(8)) |
| #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN BIT(10) |
| /* |
| * MT8195_VDO0_SOUT[11:11]: VPP_MERGE |
| * 0 : DSC_WRAP1_IN |
| */ |
| #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN 0 |
| /* |
| * MT8195_VDO0_SOUT[13:12]: DSC_WRAP0_OUT |
| * 0 : DSI0 |
| * 1 : SINB_VIRTUAL0 |
| * 2 : VPP_MERGE |
| */ |
| #define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 0 |
| #define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 BIT(12) |
| #define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(13) |
| /* |
| * MT8195_VDO0_SOUT[17:16]: DSC_WRAP1_OUT |
| * 0 : DSI1 |
| * 1 : DP_INTF0 |
| * 2 : SINA_VIRTUAL0 |
| * 3 : VPP_MERGE |
| */ |
| #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 0 |
| #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 BIT(16) |
| #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 BIT(17) |
| #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (BIT(17) | BIT(16)) |
| |
| #define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 |
| #define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 |
| |
| #define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 |
| #define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 |
| |
| #define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10 |
| #define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 |
| |
| #define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 |
| #define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 |
| |
| #define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18 |
| #define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2 |
| #define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3 |
| |
| #define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24 |
| #define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 |
| |
| #define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28 |
| #define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 |
| |
| #define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c |
| #define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 |
| |
| #define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30 |
| #define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 |
| |
| #define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34 |
| #define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 |
| |
| #define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c |
| #define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 |
| |
| #define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 |
| #define MT8195_SOUT_TO_MIXER_IN1_SEL 1 |
| |
| #define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 |
| #define MT8195_SOUT_TO_MIXER_IN2_SEL 1 |
| |
| #define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 |
| #define MT8195_SOUT_TO_MIXER_IN3_SEL 1 |
| |
| #define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c |
| #define MT8195_SOUT_TO_MIXER_IN4_SEL 1 |
| |
| #define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 |
| #define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 |
| |
| #define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58 |
| #define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0 |
| |
| #define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c |
| #define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0 |
| |
| #define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60 |
| #define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0 |
| |
| #define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64 |
| #define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0 |
| |
| #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 |
| #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 |
| |
| #define MT8195_VDO1_SW0_RST_B 0x1d0 |
| #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 |
| #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40 |
| #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50 |
| #define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60 |
| #define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 |
| #define MT8195_VDO1_HDR_TOP_CFG 0xd00 |
| #define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30 |
| #define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34 |
| #define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38 |
| #define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c |
| #define MT8195_VDO1_MIXER_IN1_PAD 0xd40 |
| #define MT8195_VDO1_MIXER_IN2_PAD 0xd44 |
| #define MT8195_VDO1_MIXER_IN3_PAD 0xd48 |
| #define MT8195_VDO1_MIXER_IN4_PAD 0xd4c |
| |
| /* VPPSYS0 MOUT */ |
| #define MT8195_VPPSYS0_STITCH_MOUT_EN 0xF38 |
| #define MT8195_VPPSYS0_STITCH_MOUT_TO_PQ_SEL_IN BIT(0) |
| #define MT8195_VPPSYS0_STITCH_MOUT_TO_VPP1_SEL_IN BIT(1) |
| #define MT8195_VPPSYS0_WARP0_MOUT_EN 0xF3C |
| #define MT8195_VPPSYS0_WARP0_MOUT_TO_PQ_SEL_IN BIT(0) |
| #define MT8195_VPPSYS0_WARP0_MOUT_TO_VPP1_SEL_IN BIT(1) |
| #define MT8195_VPPSYS0_WARP1_MOUT_EN 0xF40 |
| #define MT8195_VPPSYS0_WARP1_MOUT_TO_PQ_SEL_IN BIT(0) |
| #define MT8195_VPPSYS0_WARP1_MOUT_TO_VPP1_SEL_IN BIT(1) |
| #define MT8195_VPPSYS0_FG_MOUT_EN 0xF44 |
| #define MT8195_VPPSYS0_FG_MOUT_TO_PQ_SEL_IN BIT(0) |
| #define MT8195_VPPSYS0_FG_MOUT_TO_VPP1_SEL_IN BIT(1) |
| |
| /* VPPSYS1 MOUT */ |
| #define MT8195_SVPP2_SRC_SEL_MOUT_EN 0xF50 |
| #define MT8195_SVPP2_MDP_HDR BIT(0) |
| #define MT8195_SVPP1_HDR_SRC_SEL BIT(1) |
| #define MT8195_SVPP3_SRC_SEL_MOUT_EN 0xF7C |
| #define MT8195_SVPP3_MDP_HDR BIT(0) |
| #define MT8195_VPP0_DL1_SRC_SEL BIT(1) |
| #define MT8195_SVPP2_MDP_HDR_MOUT_EN 0xF4C |
| #define MT8195_SVPP2_MDP_AAL BIT(0) |
| #define MT8195_SVPP1_MDP_AAL_SEL BIT(1) |
| #define MT8195_SVPP3_MDP_HDR_MOUT_EN 0xF78 |
| #define MT8195_SVPP3_MDP_AAL BIT(0) |
| |
| /* VPPSYS0 SEL_IN */ |
| #define MT8195_VPPSYS0_PQ_SEL_IN 0xF04 |
| #define MT8195_VPPSYS0_PQ_SEL_IN_FROM_STITCH 0 |
| #define MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP0 1 |
| #define MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP1 2 |
| #define MT8195_VPPSYS0_PQ_SEL_IN_FROM_MDP_FG 3 |
| #define MT8195_VPPSYS0_VPP1_SEL_IN 0xF08 |
| #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_PADDING_SOUT 0 |
| #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_STITCH 1 |
| #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP0 2 |
| #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP1 3 |
| #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_MDP_FG 4 |
| #define MT8195_VPPSYS0_HDR_SEL_IN 0xF0C |
| #define MT8195_VPPSYS0_HDR_SEL_IN_FROM_PQ_SOUT 0 |
| #define MT8195_VPPSYS0_HDR_SEL_IN_FROM_TCC_SOUT 1 |
| #define MT8195_VPPSYS0_HDR_SEL_IN_FROM_VPP1_IN_SOUT 2 |
| #define MT8195_VPPSYS0_AAL_SEL_IN 0xF18 |
| #define MT8195_VPPSYS0_AAL_SEL_IN_FROM_MDP_HDR 0 |
| #define MT8195_VPPSYS0_AAL_SEL_IN_FROM_VPP1_IN_SOUT 1 |
| #define MT8195_VPPSYS0_TCC_SEL_IN 0xF10 |
| #define MT8195_VPPSYS0_TCC_SEL_IN_FROM_PADDING_SOUT 0 |
| #define MT8195_VPPSYS0_TCC_SEL_IN_FROM_PQ_SOUT 1 |
| #define MT8195_VPPSYS0_WROT_SEL_IN 0xF14 |
| #define MT8195_VPPSYS0_WROT_SEL_IN_FROM_TCC_SOUT 0 |
| #define MT8195_VPPSYS0_WROT_SEL_IN_FROM_PADDING_SOUT 1 |
| #define MT8195_VPPSYS0_WROT_SEL_IN_FROM_MDP_RDMA 2 |
| |
| /* VPPSYS1 SEL_IN */ |
| #define MT8195_SVPP1_SRC_SEL_IN 0xF1C |
| #define MT8195_SVPP1_SRC_SEL_IN_FROM_SVPP1_MDP_FG 0 |
| #define MT8195_SVPP1_SRC_SEL_IN_FROM_VPP0_SRC_SOUT 1 |
| #define MT8195_SVPP2_SRC_SEL_IN 0xF38 |
| #define MT8195_SVPP2_SRC_SEL_IN_FROM_SVPP2_MDP_FG 0 |
| #define MT8195_SVPP2_SRC_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT 1 |
| #define MT8195_SVPP3_SRC_SEL_IN 0xF64 |
| #define MT8195_SVPP3_SRC_SEL_IN_FROM_SVPP3_MDP_FG 0 |
| #define MT8195_SVPP3_SRC_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT 1 |
| #define MT8195_SVPP1_HDR_SRC_SEL_IN 0xF24 |
| #define MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT 0 |
| #define MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT 1 |
| #define MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP2_SRC_SEL_MOUT 2 |
| #define MT8195_SVPP1_MDP_AAL_SEL_IN 0xF54 |
| #define MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP1_MDP_HDR 0 |
| #define MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP2_MDP_HDR_MOUT 1 |
| #define MT8195_SVPP1_TCC_SEL_IN 0xF30 |
| #define MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_PATH_SOUT 0 |
| #define MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT 1 |
| #define MT8195_VPP0_DL1_SRC_SEL_IN 0xF80 |
| #define MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_SRC_SEL_MOUT 0 |
| #define MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_MDP_HDR_MOUT 1 |
| #define MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT 2 |
| #define MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN 0xF44 |
| #define MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_SVPP2_MDP_AAL 0 |
| #define MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT 1 |
| #define MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN 0xF70 |
| #define MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_SVPP3_MDP_AAL 0 |
| #define MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT 1 |
| #define MT8195_SVPP1_WROT_SRC_SEL_IN 0xF2c |
| #define MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT 0 |
| #define MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT 1 |
| #define MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_MDP_RDMA_SOUT 2 |
| #define MT8195_SVPP2_WROT_SRC_SEL_IN 0xF40 |
| #define MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT 0 |
| #define MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_VPP_PAD 1 |
| #define MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_MDP_RDMA_SOUT 2 |
| #define MT8195_SVPP3_WROT_SRC_SEL_IN 0xF6c |
| #define MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_VPP0_SRC_SOUT 0 |
| #define MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_VPP_PAD 1 |
| #define MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_MDP_RDMA_SOUT 2 |
| |
| /* VPPSYS0 SEL_OUT */ |
| #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN 0xF20 |
| #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH 0 |
| #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP0_MOUT 1 |
| #define MT8195_VPPSYS0_WARP1_SOUT_SEL_IN 0xF24 |
| #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH 0 |
| #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP1_MOUT 1 |
| #define MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN 0xF1C |
| #define MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_FG 0 |
| #define MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_WROT_SEL_IN 1 |
| #define MT8195_VPPSYS0_PQ_SOUT_SEL_IN 0xF28 |
| #define MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_PQ_SEL_IN 0 |
| #define MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_TCC_SEL_IN 1 |
| #define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN 0xF34 |
| #define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_HDR_SEL_IN 0 |
| #define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_AAL_SEL_IN 1 |
| #define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_MDP_RSZ 2 |
| #define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN 0xF2C |
| #define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_TCC_SEL_IN 0 |
| #define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_WROT_SEL_IN 1 |
| #define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_VPP1_SEL_IN 2 |
| #define MT8195_VPPSYS0_TCC_SOUT_SEL_IN 0xF30 |
| #define MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_WROT_SEL_IN 0 |
| #define MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_HDR_SEL_IN 1 |
| |
| /* VPPSYS1 SEL_OUT */ |
| #define MT8195_SVPP1_MDP_RDMA_SOUT_SEL 0xF18 |
| #define MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_MDP_FG 0 |
| #define MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_RSZ 1 |
| #define MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL 2 |
| #define MT8195_SVPP2_MDP_RDMA_SOUT_SEL 0xF90 |
| #define MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_FG 0 |
| #define MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL 1 |
| #define MT8195_SVPP3_MDP_RDMA_SOUT_SEL 0xF60 |
| #define MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_MDP_FG 0 |
| #define MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL 1 |
| #define MT8195_VPP0_SRC_SOUT_SEL 0xF8C |
| #define MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP1_SRC_SEL 0 |
| #define MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_MDP_RSZ 1 |
| #define MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL 2 |
| #define MT8195_SVPP1_SRC_SEL_SOUT_SEL 0xF20 |
| #define MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL 0 |
| #define MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_TCC_SEL 1 |
| #define MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_VPP0_DL1_SRC_SEL 2 |
| #define MT8195_SVPP2_COLOR_SOUT_SEL 0xF3c |
| #define MT8195_SVPP2_COLOR_SOUT_SEL_TO_SVPP2_VPP_PAD 0 |
| #define MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO0_DL0_RELAY 1 |
| #define MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO1_DL0_RELAY 2 |
| #define MT8195_SVPP3_COLOR_SOUT_SEL 0xF68 |
| #define MT8195_SVPP3_COLOR_SOUT_SEL_TO_SVPP3_VPP_PAD 0 |
| #define MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO0_DL1_RELAY 1 |
| #define MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO1_DL1_RELAY 2 |
| #define MT8195_SVPP1_TCC_SOUT_SEL 0xF34 |
| #define MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL 0 |
| #define MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL 1 |
| #define MT8195_SVPP1_PATH_SOUT_SEL 0xF28 |
| #define MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_TCC_SEL 0 |
| #define MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL 1 |
| #define MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL 2 |
| |
| /* VPPSYS0 */ |
| #define VPPSYS0_HW_DCM_1ST_DIS0 0x050 |
| |
| /* VPPSYS1 */ |
| #define VPPSYS1_HW_DCM_1ST_DIS0 0x150 |
| #define VPPSYS1_HW_DCM_1ST_DIS1 0x160 |
| #define VPPSYS1_HW_DCM_2ND_DIS0 0x1a0 |
| #define VPPSYS1_HW_DCM_2ND_DIS1 0x1b0 |
| #define VPP0_DL_IRELAY_WR 0x920 |
| #define SVPP2_BUF_BF_RSZ_SWITCH 0xf48 |
| #define SVPP3_BUF_BF_RSZ_SWITCH 0xf74 |
| |
| static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { |
| { |
| DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, |
| MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, |
| MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 |
| }, { |
| DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, |
| MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, |
| MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 |
| }, { |
| DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, |
| MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT, |
| MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT |
| }, { |
| DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, |
| MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE, |
| MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE |
| }, { |
| DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0, |
| MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0, |
| MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 |
| }, { |
| DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, |
| MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT, |
| MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT |
| }, { |
| DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, |
| MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0, |
| MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 |
| }, { |
| DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0, |
| MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN, |
| MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN |
| }, { |
| DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, |
| MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSI0, |
| MT8195_SOUT_DISP_DITHER0_TO_DSI0 |
| }, { |
| DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, |
| MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0, |
| MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 |
| }, { |
| DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, |
| MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE, |
| MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE |
| }, { |
| DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, |
| MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DP_INTF0, |
| MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), |
| MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), |
| MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), |
| MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), |
| MT8195_SOUT_TO_MIXER_IN1_SEL |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), |
| MT8195_SOUT_TO_MIXER_IN2_SEL |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), |
| MT8195_SOUT_TO_MIXER_IN3_SEL |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), |
| MT8195_SOUT_TO_MIXER_IN4_SEL |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), |
| MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), |
| MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), |
| MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), |
| MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), |
| MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), |
| MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER |
| }, { |
| DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, |
| MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), |
| MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT |
| }, { |
| DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, |
| MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), |
| MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT |
| }, { |
| DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, |
| MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), |
| MT8195_MERGE4_SOUT_TO_DPI1_SEL |
| }, { |
| DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, |
| MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), |
| MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT |
| }, { |
| DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, |
| MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), |
| MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL |
| } |
| }; |
| |
| |
| /* |
| * mtk_mmsys_config table is used for config mmsys reg in runtime. |
| * MMSYS_CONFIG_MERGE_ASYNC_WIDTH: config merge async width |
| * MMSYS_CONFIG_MERGE_ASYNC_HEIGHT: config merge async height |
| * MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH: config hdr_be async width |
| * MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT: config hdr_be async height |
| * MMSYS_CONFIG_MIXER_IN_ALPHA_ODD: config mixer odd channel 9bit alpha value |
| * MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN: config mixer even channel 9bit alpha value |
| * MMSYS_CONFIG_MIXER_IN_CH_SWAP: config mixer input RGB channel swap |
| * MMSYS_CONFIG_HDR_ALPHA_SEL: config alpha source |
| * MMSYS_CONFIG_MIXER_IN_MODE: config mixer pad mode(bypass/even extend mode) |
| * MMSYS_CONFIG_MIXER_IN_BIWIDTH: config mixer pad width. formula: width / 2 - 1 |
| */ |
| static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = { |
| { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0}, |
| { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16}, |
| { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0}, |
| { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16}, |
| { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0}, |
| { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16}, |
| { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0}, |
| { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16}, |
| { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0}, |
| { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16}, |
| { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0}, |
| { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16}, |
| { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0}, |
| { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16}, |
| { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0}, |
| { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16}, |
| { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0}, |
| { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16}, |
| { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4}, |
| { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20}, |
| { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21}, |
| { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22}, |
| { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23}, |
| { MMSYS_CONFIG_MIXER_IN_MODE, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(1, 0), 0}, |
| { MMSYS_CONFIG_MIXER_IN_MODE, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(1, 0), 0}, |
| { MMSYS_CONFIG_MIXER_IN_MODE, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(1, 0), 0}, |
| { MMSYS_CONFIG_MIXER_IN_MODE, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(1, 0), 0}, |
| { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(31, 16), 16}, |
| { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(31, 16), 16}, |
| { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(31, 16), 16}, |
| { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(31, 16), 16}, |
| }; |
| |
| static const u32 mmsys_mt8195_mdp_vppsys_config_table[] = { |
| VPPSYS0_HW_DCM_1ST_DIS0, |
| VPP0_DL_IRELAY_WR, |
| VPPSYS1_HW_DCM_1ST_DIS0, |
| VPPSYS1_HW_DCM_1ST_DIS1, |
| VPPSYS1_HW_DCM_2ND_DIS0, |
| VPPSYS1_HW_DCM_2ND_DIS1, |
| SVPP2_BUF_BF_RSZ_SWITCH, |
| SVPP3_BUF_BF_RSZ_SWITCH, |
| }; |
| |
| #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ |
