| /* |
| * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| #include <dt-bindings/bus/ti-sysc.h> |
| #include <dt-bindings/clock/omap4.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/pinctrl/omap.h> |
| #include <dt-bindings/clock/omap4.h> |
| |
| / { |
| compatible = "ti,omap4430", "ti,omap4"; |
| interrupt-parent = <&wakeupgen>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| chosen { }; |
| |
| aliases { |
| i2c0 = &i2c1; |
| i2c1 = &i2c2; |
| i2c2 = &i2c3; |
| i2c3 = &i2c4; |
| mmc0 = &mmc1; |
| mmc1 = &mmc2; |
| mmc2 = &mmc3; |
| mmc3 = &mmc4; |
| mmc4 = &mmc5; |
| serial0 = &uart1; |
| serial1 = &uart2; |
| serial2 = &uart3; |
| serial3 = &uart4; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "arm,cortex-a9"; |
| device_type = "cpu"; |
| next-level-cache = <&L2>; |
| reg = <0x0>; |
| |
| clocks = <&dpll_mpu_ck>; |
| clock-names = "cpu"; |
| |
| clock-latency = <300000>; /* From omap-cpufreq driver */ |
| }; |
| cpu@1 { |
| compatible = "arm,cortex-a9"; |
| device_type = "cpu"; |
| next-level-cache = <&L2>; |
| reg = <0x1>; |
| }; |
| }; |
| |
| /* |
| * Note that 4430 needs cross trigger interface (CTI) supported |
| * before we can configure the interrupts. This means sampling |
| * events are not supported for pmu. Note that 4460 does not use |
| * CTI, see also 4460.dtsi. |
| */ |
| pmu { |
| compatible = "arm,cortex-a9-pmu"; |
| ti,hwmods = "debugss"; |
| }; |
| |
| gic: interrupt-controller@48241000 { |
| compatible = "arm,cortex-a9-gic"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0x48241000 0x1000>, |
| <0x48240100 0x0100>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| L2: l2-cache-controller@48242000 { |
| compatible = "arm,pl310-cache"; |
| reg = <0x48242000 0x1000>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| |
| local-timer@48240600 { |
| compatible = "arm,cortex-a9-twd-timer"; |
| clocks = <&mpu_periphclk>; |
| reg = <0x48240600 0x20>; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| wakeupgen: interrupt-controller@48281000 { |
| compatible = "ti,omap4-wugen-mpu"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0x48281000 0x1000>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| /* |
| * The soc node represents the soc top level view. It is used for IPs |
| * that are not memory mapped in the MPU view or for the MPU itself. |
| */ |
| soc { |
| compatible = "ti,omap-infra"; |
| mpu { |
| compatible = "ti,omap4-mpu"; |
| ti,hwmods = "mpu"; |
| sram = <&ocmcram>; |
| }; |
| |
| dsp { |
| compatible = "ti,omap3-c64"; |
| ti,hwmods = "dsp"; |
| }; |
| |
| iva { |
| compatible = "ti,ivahd"; |
| ti,hwmods = "iva"; |
| }; |
| }; |
| |
| /* |
| * XXX: Use a flat representation of the OMAP4 interconnect. |
| * The real OMAP interconnect network is quite complex. |
| * Since it will not bring real advantage to represent that in DT for |
| * the moment, just use a fake OCP bus entry to represent the whole bus |
| * hierarchy. |
| */ |
| ocp { |
| compatible = "ti,omap4-l3-noc", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
| reg = <0x44000000 0x1000>, |
| <0x44800000 0x2000>, |
| <0x45000000 0x1000>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| |
| l4_wkup: interconnect@4a300000 { |
| }; |
| |
| l4_cfg: interconnect@4a000000 { |
| }; |
| |
| l4_per: interconnect@48000000 { |
| }; |
| |
| ocmcram: ocmcram@40304000 { |
| compatible = "mmio-sram"; |
| reg = <0x40304000 0xa000>; /* 40k */ |
| }; |
| |
| gpmc: gpmc@50000000 { |
| compatible = "ti,omap4430-gpmc"; |
| reg = <0x50000000 0x1000>; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&sdma 4>; |
| dma-names = "rxtx"; |
| gpmc,num-cs = <8>; |
| gpmc,num-waitpins = <4>; |
| ti,hwmods = "gpmc"; |
| ti,no-idle-on-init; |
| clocks = <&l3_div_ck>; |
| clock-names = "fck"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| mmu_dsp: mmu@4a066000 { |
| compatible = "ti,omap4-iommu"; |
| reg = <0x4a066000 0x100>; |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mmu_dsp"; |
| #iommu-cells = <0>; |
| }; |
| |
| target-module@52000000 { |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| ti,hwmods = "iss"; |
| reg = <0x52000000 0x4>, |
| <0x52000010 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-delay-us = <2>; |
| clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x52000000 0x1000000>; |
| |
| /* No child device binding, driver in staging */ |
| }; |
| |
| mmu_ipu: mmu@55082000 { |
| compatible = "ti,omap4-iommu"; |
| reg = <0x55082000 0x100>; |
| interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mmu_ipu"; |
| #iommu-cells = <0>; |
| ti,iommu-bus-err-back; |
| }; |
| target-module@40130000 { |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| ti,hwmods = "wd_timer3"; |
| reg = <0x40130000 0x4>, |
| <0x40130010 0x4>, |
| <0x40130014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | |
| SYSC_OMAP2_SOFTRESET)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (V, P, C): abe, abe_pwrdm, abe_clkdm */ |
| clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x40130000 0x1000>, /* MPU private access */ |
| <0x49030000 0x49030000 0x0080>; /* L3 Interconnect */ |
| |
| wdt3: wdt@0 { |
| compatible = "ti,omap4-wdt", "ti,omap3-wdt"; |
| reg = <0x0 0x80>; |
| interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| mcpdm: mcpdm@40132000 { |
| compatible = "ti,omap4-mcpdm"; |
| reg = <0x40132000 0x7f>, /* MPU private access */ |
| <0x49032000 0x7f>; /* L3 Interconnect */ |
| reg-names = "mpu", "dma"; |
| interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "mcpdm"; |
| dmas = <&sdma 65>, |
| <&sdma 66>; |
| dma-names = "up_link", "dn_link"; |
| status = "disabled"; |
| }; |
| |
| dmic: dmic@4012e000 { |
| compatible = "ti,omap4-dmic"; |
| reg = <0x4012e000 0x7f>, /* MPU private access */ |
| <0x4902e000 0x7f>; /* L3 Interconnect */ |
| reg-names = "mpu", "dma"; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "dmic"; |
| dmas = <&sdma 67>; |
| dma-names = "up_link"; |
| status = "disabled"; |
| }; |
| |
| mcbsp1: mcbsp@40122000 { |
| compatible = "ti,omap4-mcbsp"; |
| reg = <0x40122000 0xff>, /* MPU private access */ |
| <0x49022000 0xff>; /* L3 Interconnect */ |
| reg-names = "mpu", "dma"; |
| interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "common"; |
| ti,buffer-size = <128>; |
| ti,hwmods = "mcbsp1"; |
| dmas = <&sdma 33>, |
| <&sdma 34>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| mcbsp2: mcbsp@40124000 { |
| compatible = "ti,omap4-mcbsp"; |
| reg = <0x40124000 0xff>, /* MPU private access */ |
| <0x49024000 0xff>; /* L3 Interconnect */ |
| reg-names = "mpu", "dma"; |
| interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "common"; |
| ti,buffer-size = <128>; |
| ti,hwmods = "mcbsp2"; |
| dmas = <&sdma 17>, |
| <&sdma 18>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| mcbsp3: mcbsp@40126000 { |
| compatible = "ti,omap4-mcbsp"; |
| reg = <0x40126000 0xff>, /* MPU private access */ |
| <0x49026000 0xff>; /* L3 Interconnect */ |
| reg-names = "mpu", "dma"; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "common"; |
| ti,buffer-size = <128>; |
| ti,hwmods = "mcbsp3"; |
| dmas = <&sdma 19>, |
| <&sdma 20>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| target-module@40128000 { |
| compatible = "ti,sysc-mcasp", "ti,sysc"; |
| ti,hwmods = "mcasp"; |
| reg = <0x40128000 0x4>, |
| <0x40128004 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x40128000 0x1000>, /* MPU */ |
| <0x49028000 0x49028000 0x1000>; /* L3 */ |
| |
| /* |
| * Child device unsupported by davinci-mcasp. At least |
| * RX path is disabled for omap4, and only DIT mode |
| * works with no I2S. See also old Android kernel |
| * omap-mcasp driver for more information. |
| */ |
| }; |
| |
| target-module@4012c000 { |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| ti,hwmods = "slimbus1"; |
| reg = <0x4012c000 0x4>, |
| <0x4012c010 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */ |
| <0x4902c000 0x4902c000 0x1000>; /* L3 */ |
| |
| /* No child device binding or driver in mainline */ |
| }; |
| |
| target-module@401f1000 { |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| ti,hwmods = "aess"; |
| reg = <0x401f1000 0x4>, |
| <0x401f1010 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */ |
| <0x490f1000 0x490f1000 0x1000>; /* L3 */ |
| |
| /* |
| * No child device binding or driver in mainline. |
| * See Android tree and related upstreaming efforts |
| * for the old driver. |
| */ |
| }; |
| |
| dmm@4e000000 { |
| compatible = "ti,omap4-dmm"; |
| reg = <0x4e000000 0x800>; |
| interrupts = <0 113 0x4>; |
| ti,hwmods = "dmm"; |
| }; |
| |
| emif1: emif@4c000000 { |
| compatible = "ti,emif-4d"; |
| reg = <0x4c000000 0x100>; |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "emif1"; |
| ti,no-idle-on-init; |
| phy-type = <1>; |
| hw-caps-read-idle-ctrl; |
| hw-caps-ll-interface; |
| hw-caps-temp-alert; |
| }; |
| |
| emif2: emif@4d000000 { |
| compatible = "ti,emif-4d"; |
| reg = <0x4d000000 0x100>; |
| interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "emif2"; |
| ti,no-idle-on-init; |
| phy-type = <1>; |
| hw-caps-read-idle-ctrl; |
| hw-caps-ll-interface; |
| hw-caps-temp-alert; |
| }; |
| |
| timer5: timer@40138000 { |
| compatible = "ti,omap4430-timer"; |
| reg = <0x40138000 0x80>, |
| <0x49038000 0x80>; |
| interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer5"; |
| ti,timer-dsp; |
| }; |
| |
| timer6: timer@4013a000 { |
| compatible = "ti,omap4430-timer"; |
| reg = <0x4013a000 0x80>, |
| <0x4903a000 0x80>; |
| interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer6"; |
| ti,timer-dsp; |
| }; |
| |
| timer7: timer@4013c000 { |
| compatible = "ti,omap4430-timer"; |
| reg = <0x4013c000 0x80>, |
| <0x4903c000 0x80>; |
| interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer7"; |
| ti,timer-dsp; |
| }; |
| |
| timer8: timer@4013e000 { |
| compatible = "ti,omap4430-timer"; |
| reg = <0x4013e000 0x80>, |
| <0x4903e000 0x80>; |
| interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "timer8"; |
| ti,timer-pwm; |
| ti,timer-dsp; |
| }; |
| |
| aes1: aes@4b501000 { |
| compatible = "ti,omap4-aes"; |
| ti,hwmods = "aes1"; |
| reg = <0x4b501000 0xa0>; |
| interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&sdma 111>, <&sdma 110>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| aes2: aes@4b701000 { |
| compatible = "ti,omap4-aes"; |
| ti,hwmods = "aes2"; |
| reg = <0x4b701000 0xa0>; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&sdma 114>, <&sdma 113>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| des: des@480a5000 { |
| compatible = "ti,omap4-des"; |
| ti,hwmods = "des"; |
| reg = <0x480a5000 0xa0>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&sdma 117>, <&sdma 116>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| sham: sham@4b100000 { |
| compatible = "ti,omap4-sham"; |
| ti,hwmods = "sham"; |
| reg = <0x4b100000 0x300>; |
| interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&sdma 119>; |
| dma-names = "rx"; |
| }; |
| |
| abb_mpu: regulator-abb-mpu { |
| compatible = "ti,abb-v2"; |
| regulator-name = "abb_mpu"; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| ti,tranxdone-status-mask = <0x80>; |
| clocks = <&sys_clkin_ck>; |
| ti,settling-time = <50>; |
| ti,clock-cycles = <16>; |
| |
| status = "disabled"; |
| }; |
| |
| abb_iva: regulator-abb-iva { |
| compatible = "ti,abb-v2"; |
| regulator-name = "abb_iva"; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| ti,tranxdone-status-mask = <0x80000000>; |
| clocks = <&sys_clkin_ck>; |
| ti,settling-time = <50>; |
| ti,clock-cycles = <16>; |
| |
| status = "disabled"; |
| }; |
| |
| sgx_module: target-module@56000000 { |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| ti,hwmods = "gpu"; |
| reg = <0x5601fc00 0x4>, |
| <0x5601fc10 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x56000000 0x2000000>; |
| |
| /* |
| * Closed source PowerVR driver, no child device |
| * binding or driver in mainline |
| */ |
| }; |
| |
| dss: dss@58000000 { |
| compatible = "ti,omap4-dss"; |
| reg = <0x58000000 0x80>; |
| status = "disabled"; |
| ti,hwmods = "dss_core"; |
| clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| dispc@58001000 { |
| compatible = "ti,omap4-dispc"; |
| reg = <0x58001000 0x1000>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "dss_dispc"; |
| clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; |
| clock-names = "fck"; |
| }; |
| |
| rfbi: encoder@58002000 { |
| compatible = "ti,omap4-rfbi"; |
| reg = <0x58002000 0x1000>; |
| status = "disabled"; |
| ti,hwmods = "dss_rfbi"; |
| clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>; |
| clock-names = "fck", "ick"; |
| }; |
| |
| venc: encoder@58003000 { |
| compatible = "ti,omap4-venc"; |
| reg = <0x58003000 0x1000>; |
| status = "disabled"; |
| ti,hwmods = "dss_venc"; |
| clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; |
| clock-names = "fck"; |
| }; |
| |
| dsi1: encoder@58004000 { |
| compatible = "ti,omap4-dsi"; |
| reg = <0x58004000 0x200>, |
| <0x58004200 0x40>, |
| <0x58004300 0x20>; |
| reg-names = "proto", "phy", "pll"; |
| interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| ti,hwmods = "dss_dsi1"; |
| clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, |
| <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; |
| clock-names = "fck", "sys_clk"; |
| }; |
| |
| dsi2: encoder@58005000 { |
| compatible = "ti,omap4-dsi"; |
| reg = <0x58005000 0x200>, |
| <0x58005200 0x40>, |
| <0x58005300 0x20>; |
| reg-names = "proto", "phy", "pll"; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| ti,hwmods = "dss_dsi2"; |
| clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, |
| <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; |
| clock-names = "fck", "sys_clk"; |
| }; |
| |
| hdmi: encoder@58006000 { |
| compatible = "ti,omap4-hdmi"; |
| reg = <0x58006000 0x200>, |
| <0x58006200 0x100>, |
| <0x58006300 0x100>, |
| <0x58006400 0x1000>; |
| reg-names = "wp", "pll", "phy", "core"; |
| interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| ti,hwmods = "dss_hdmi"; |
| clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, |
| <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; |
| clock-names = "fck", "sys_clk"; |
| dmas = <&sdma 76>; |
| dma-names = "audio_tx"; |
| }; |
| }; |
| }; |
| }; |
| |
| #include "omap4-l4.dtsi" |
| #include "omap44xx-clocks.dtsi" |
