| NVIDIA Tegra Video Decoder Engine |
| |
| Required properties: |
| - compatible : Must contain one of the following values: |
| - "nvidia,tegra20-vde" |
| - "nvidia,tegra30-vde" |
| - "nvidia,tegra114-vde" |
| - "nvidia,tegra124-vde" |
| - "nvidia,tegra132-vde" |
| - reg : Must contain an entry for each entry in reg-names. |
| - reg-names : Must include the following entries: |
| - sxe |
| - bsev |
| - mbe |
| - ppe |
| - mce |
| - tfe |
| - ppb |
| - vdma |
| - frameid |
| - iram : Must contain phandle to the mmio-sram device node that represents |
| IRAM region used by VDE. |
| - interrupts : Must contain an entry for each entry in interrupt-names. |
| - interrupt-names : Must include the following entries: |
| - sync-token |
| - bsev |
| - sxe |
| - clocks : Must include the following entries: |
| - vde |
| - resets : Must include the following entries: |
| - vde |
| |
| Example: |
| |
| video-codec@6001a000 { |
| compatible = "nvidia,tegra20-vde"; |
| reg = <0x6001a000 0x1000 /* Syntax Engine */ |
| 0x6001b000 0x1000 /* Video Bitstream Engine */ |
| 0x6001c000 0x100 /* Macroblock Engine */ |
| 0x6001c200 0x100 /* Post-processing Engine */ |
| 0x6001c400 0x100 /* Motion Compensation Engine */ |
| 0x6001c600 0x100 /* Transform Engine */ |
| 0x6001c800 0x100 /* Pixel prediction block */ |
| 0x6001ca00 0x100 /* Video DMA */ |
| 0x6001d800 0x300 /* Video frame controls */>; |
| reg-names = "sxe", "bsev", "mbe", "ppe", "mce", |
| "tfe", "ppb", "vdma", "frameid"; |
| iram = <&vde_pool>; /* IRAM region */ |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ |
| <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ |
| <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ |
| interrupt-names = "sync-token", "bsev", "sxe"; |
| clocks = <&tegra_car TEGRA20_CLK_VDE>; |
| resets = <&tegra_car 61>; |
| }; |
