| Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks |
| |
| TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of |
| registers call CFGCHIPn. Some of these registers function as clock |
| gates. This document describes the bindings for those clocks. |
| |
| All of the clock nodes described below must be child nodes of a CFGCHIP node |
| (compatible = "ti,da830-cfgchip"). |
| |
| USB PHY clocks |
| -------------- |
| Required properties: |
| - compatible: shall be "ti,da830-usb-phy-clocks". |
| - #clock-cells: from common clock binding; shall be set to 1. |
| - clocks: phandles to the parent clocks corresponding to clock-names |
| - clock-names: shall be "fck", "usb_refclkin", "auxclk" |
| |
| This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz |
| clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock. |
| |
| eHRPWM Time Base Clock (TBCLK) |
| ------------------------------ |
| Required properties: |
| - compatible: shall be "ti,da830-tbclksync". |
| - #clock-cells: from common clock binding; shall be set to 0. |
| - clocks: phandle to the parent clock |
| - clock-names: shall be "fck" |
| |
| PLL DIV4.5 divider |
| ------------------ |
| Required properties: |
| - compatible: shall be "ti,da830-div4p5ena". |
| - #clock-cells: from common clock binding; shall be set to 0. |
| - clocks: phandle to the parent clock |
| - clock-names: shall be "pll0_pllout" |
| |
| EMIFA clock source (ASYNC1) |
| --------------------------- |
| Required properties: |
| - compatible: shall be "ti,da850-async1-clksrc". |
| - #clock-cells: from common clock binding; shall be set to 0. |
| - clocks: phandles to the parent clocks corresponding to clock-names |
| - clock-names: shall be "pll0_sysclk3", "div4.5" |
| |
| ASYNC3 clock source |
| ------------------- |
| Required properties: |
| - compatible: shall be "ti,da850-async3-clksrc". |
| - #clock-cells: from common clock binding; shall be set to 0. |
| - clocks: phandles to the parent clocks corresponding to clock-names |
| - clock-names: shall be "pll0_sysclk2", "pll1_sysclk2" |
| |
| Examples: |
| |
| cfgchip: syscon@1417c { |
| compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; |
| reg = <0x1417c 0x14>; |
| |
| usb_phy_clk: usb-phy-clocks { |
| compatible = "ti,da830-usb-phy-clocks"; |
| #clock-cells = <1>; |
| clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>; |
| clock-names = "fck", "usb_refclkin", "auxclk"; |
| }; |
| ehrpwm_tbclk: ehrpwm_tbclk { |
| compatible = "ti,da830-tbclksync"; |
| #clock-cells = <0>; |
| clocks = <&psc1 17>; |
| clock-names = "fck"; |
| }; |
| div4p5_clk: div4.5 { |
| compatible = "ti,da830-div4p5ena"; |
| #clock-cells = <0>; |
| clocks = <&pll0_pllout>; |
| clock-names = "pll0_pllout"; |
| }; |
| async1_clk: async1 { |
| compatible = "ti,da850-async1-clksrc"; |
| #clock-cells = <0>; |
| clocks = <&pll0_sysclk 3>, <&div4p5_clk>; |
| clock-names = "pll0_sysclk3", "div4.5"; |
| }; |
| async3_clk: async3 { |
| compatible = "ti,da850-async3-clksrc"; |
| #clock-cells = <0>; |
| clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; |
| clock-names = "pll0_sysclk2", "pll1_sysclk2"; |
| }; |
| }; |
| |
| Also see: |
| - Documentation/devicetree/bindings/clock/clock-bindings.txt |
| |
