| [ |
| { |
| "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5", |
| "EventCode": "0x08", |
| "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", |
| "PEBScounters": "0,1,2,3,4,5", |
| "SampleAfterValue": "200003", |
| "Speculative": "1", |
| "UMask": "0xe", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5", |
| "EventCode": "0x49", |
| "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", |
| "PEBScounters": "0,1,2,3,4,5", |
| "SampleAfterValue": "2000003", |
| "Speculative": "1", |
| "UMask": "0xe", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5", |
| "EventCode": "0x85", |
| "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", |
| "PEBScounters": "0,1,2,3,4,5", |
| "SampleAfterValue": "1000003", |
| "Speculative": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5", |
| "EventCode": "0x85", |
| "EventName": "ITLB_MISSES.PDE_CACHE_MISS", |
| "PEBScounters": "0,1,2,3,4,5", |
| "SampleAfterValue": "2000003", |
| "Speculative": "1", |
| "UMask": "0x80", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5", |
| "EventCode": "0x85", |
| "EventName": "ITLB_MISSES.WALK_COMPLETED", |
| "PEBScounters": "0,1,2,3,4,5", |
| "SampleAfterValue": "200003", |
| "Speculative": "1", |
| "UMask": "0xe", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5", |
| "EventCode": "0x05", |
| "EventName": "LD_HEAD.DTLB_MISS_AT_RET", |
| "PEBScounters": "0,1,2,3,4,5", |
| "SampleAfterValue": "1000003", |
| "Speculative": "1", |
| "UMask": "0x90", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Loads that miss the DTLB and hit the STLB.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x12", |
| "EventName": "DTLB_LOAD_MISSES.STLB_HIT", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x20", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x12", |
| "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x10", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x12", |
| "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0xe", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x12", |
| "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x8", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x12", |
| "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x4", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x12", |
| "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x2", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x12", |
| "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x10", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Stores that miss the DTLB and hit the STLB.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x13", |
| "EventName": "DTLB_STORE_MISSES.STLB_HIT", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x20", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x13", |
| "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x10", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x13", |
| "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0xe", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Page walks completed due to a demand data store to a 1G page.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x13", |
| "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x8", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x13", |
| "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x4", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x13", |
| "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x2", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x13", |
| "EventName": "DTLB_STORE_MISSES.WALK_PENDING", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x10", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "ITLB_MISSES.STLB_HIT", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x20", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x11", |
| "EventName": "ITLB_MISSES.WALK_ACTIVE", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x10", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "ITLB_MISSES.WALK_COMPLETED", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0xe", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x4", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x2", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x11", |
| "EventName": "ITLB_MISSES.WALK_PENDING", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x10", |
| "Unit": "cpu_core" |
| } |
| ] |
