| [ |
| { |
| "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5", |
| "EventCode": "0xe6", |
| "EventName": "BACLEARS.ANY", |
| "PEBScounters": "0,1,2,3,4,5", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5", |
| "EventCode": "0x80", |
| "EventName": "ICACHE.ACCESSES", |
| "PEBScounters": "0,1,2,3,4,5", |
| "SampleAfterValue": "200003", |
| "Speculative": "1", |
| "UMask": "0x3", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of instruction cache misses.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5", |
| "EventCode": "0x80", |
| "EventName": "ICACHE.MISSES", |
| "PEBScounters": "0,1,2,3,4,5", |
| "SampleAfterValue": "200003", |
| "Speculative": "1", |
| "UMask": "0x2", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Stalls caused by changing prefix length of the instruction.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x87", |
| "EventName": "DECODE.LCP", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "500009", |
| "Speculative": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "DSB-to-MITE switch true penalty cycles.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x61", |
| "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x2", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired Instructions who experienced DSB miss.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x1", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.DSB_MISS", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x11", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired Instructions who experienced iTLB true miss.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.ITLB_MISS", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x14", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.L1I_MISS", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x12", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.L2_MISS", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x13", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x600106", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x608006", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x601006", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x600206", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x610006", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x100206", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x602006", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x600406", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x620006", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x604006", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x600806", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.MS_FLOWS", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x8", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.STLB_MISS", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x15", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc6", |
| "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", |
| "MSRIndex": "0x3F7", |
| "MSRValue": "0x17", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100007", |
| "TakenAlone": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "ICACHE_DATA.STALLS", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "500009", |
| "Speculative": "1", |
| "UMask": "0x4", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x83", |
| "EventName": "ICACHE_TAG.STALLS", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "200003", |
| "Speculative": "1", |
| "UMask": "0x4", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x79", |
| "EventName": "IDQ.DSB_CYCLES_ANY", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "2000003", |
| "Speculative": "1", |
| "UMask": "0x8", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Cycles DSB is delivering optimal number of Uops", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "CounterMask": "6", |
| "EventCode": "0x79", |
| "EventName": "IDQ.DSB_CYCLES_OK", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "2000003", |
| "Speculative": "1", |
| "UMask": "0x8", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x79", |
| "EventName": "IDQ.DSB_UOPS", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "2000003", |
| "Speculative": "1", |
| "UMask": "0x8", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Cycles MITE is delivering any Uop", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MITE_CYCLES_ANY", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "2000003", |
| "Speculative": "1", |
| "UMask": "0x4", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Cycles MITE is delivering optimal number of Uops", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "CounterMask": "6", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MITE_CYCLES_OK", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "2000003", |
| "Speculative": "1", |
| "UMask": "0x4", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MITE_UOPS", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "2000003", |
| "Speculative": "1", |
| "UMask": "0x4", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MS_CYCLES_ANY", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "2000003", |
| "Speculative": "1", |
| "UMask": "0x20", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Number of switches from DSB or MITE to the MS", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EdgeDetect": "1", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MS_SWITCHES", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x20", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Uops delivered to IDQ while MS is busy", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MS_UOPS", |
| "PEBScounters": "0,1,2,3", |
| "SampleAfterValue": "1000003", |
| "Speculative": "1", |
| "UMask": "0x20", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0x9c", |
| "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "1000003", |
| "Speculative": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "CounterMask": "6", |
| "EventCode": "0x9c", |
| "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "1000003", |
| "Speculative": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "CounterMask": "1", |
| "EventCode": "0x9c", |
| "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", |
| "Invert": "1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "1000003", |
| "Speculative": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| } |
| ] |