| // SPDX-License-Identifier: BSD-3-Clause |
| /* |
| * SDX65 SoC device tree source |
| * |
| * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. |
| * |
| */ |
| |
| #include <dt-bindings/clock/qcom,gcc-sdx65.h> |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/qcom-rpmpd.h> |
| #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
| #include <dt-bindings/interconnect/qcom,sdx65.h> |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; |
| interrupt-parent = <&intc>; |
| |
| memory { |
| device_type = "memory"; |
| reg = <0 0>; |
| }; |
| |
| clocks { |
| xo_board: xo-board { |
| compatible = "fixed-clock"; |
| clock-frequency = <76800000>; |
| clock-output-names = "xo_board"; |
| #clock-cells = <0>; |
| }; |
| |
| sleep_clk: sleep-clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <32764>; |
| clock-output-names = "sleep_clk"; |
| #clock-cells = <0>; |
| }; |
| |
| nand_clk_dummy: nand-clk-dummy { |
| compatible = "fixed-clock"; |
| clock-frequency = <32764>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| clocks = <&apcs>; |
| power-domains = <&rpmhpd SDX65_CX_AO>; |
| power-domain-names = "rpmhpd"; |
| operating-points-v2 = <&cpu_opp_table>; |
| }; |
| }; |
| |
| firmware { |
| scm { |
| compatible = "qcom,scm-sdx65", "qcom,scm"; |
| }; |
| }; |
| |
| mc_virt: interconnect-mc-virt { |
| compatible = "qcom,sdx65-mc-virt"; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| cpu_opp_table: opp-table-cpu { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp-345600000 { |
| opp-hz = /bits/ 64 <345600000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-576000000 { |
| opp-hz = /bits/ 64 <576000000>; |
| required-opps = <&rpmhpd_opp_svs>; |
| }; |
| |
| opp-1094400000 { |
| opp-hz = /bits/ 64 <1094400000>; |
| required-opps = <&rpmhpd_opp_nom>; |
| }; |
| |
| opp-1497600000 { |
| opp-hz = /bits/ 64 <1497600000>; |
| required-opps = <&rpmhpd_opp_turbo>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| reserved_memory: reserved-memory { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| tz_heap_mem: memory@8fcad000 { |
| no-map; |
| reg = <0x8fcad000 0x40000>; |
| }; |
| |
| secdata_mem: memory@8fcfd000 { |
| no-map; |
| reg = <0x8fcfd000 0x1000>; |
| }; |
| |
| hyp_mem: memory@8fd00000 { |
| no-map; |
| reg = <0x8fd00000 0x80000>; |
| }; |
| |
| access_control_mem: memory@8fd80000 { |
| no-map; |
| reg = <0x8fd80000 0x80000>; |
| }; |
| |
| aop_mem: memory@8fe00000 { |
| no-map; |
| reg = <0x8fe00000 0x20000>; |
| }; |
| |
| smem_mem: memory@8fe20000 { |
| compatible = "qcom,smem"; |
| reg = <0x8fe20000 0xc0000>; |
| hwlocks = <&tcsr_mutex 3>; |
| no-map; |
| }; |
| |
| cmd_db: reserved-memory@8fee0000 { |
| compatible = "qcom,cmd-db"; |
| reg = <0x8fee0000 0x20000>; |
| no-map; |
| }; |
| |
| tz_mem: memory@8ff00000 { |
| no-map; |
| reg = <0x8ff00000 0x100000>; |
| }; |
| |
| tz_apps_mem: memory@90000000 { |
| no-map; |
| reg = <0x90000000 0x500000>; |
| }; |
| |
| llcc_tcm_mem: memory@15800000 { |
| no-map; |
| reg = <0x15800000 0x800000>; |
| }; |
| }; |
| |
| smp2p-mpss { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <435>, <428>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&apcs 14>; |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <1>; |
| |
| modem_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| modem_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| ipa_smp2p_out: ipa-ap-to-modem { |
| qcom,entry-name = "ipa"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| ipa_smp2p_in: ipa-modem-to-ap { |
| qcom,entry-name = "ipa"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| soc: soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "simple-bus"; |
| |
| gcc: clock-controller@100000 { |
| compatible = "qcom,gcc-sdx65"; |
| reg = <0x00100000 0x001f7400>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&rpmhcc RPMH_CXO_CLK_A>, |
| <&sleep_clk>, |
| <&pcie_phy>, |
| <0>; |
| clock-names = "bi_tcxo", |
| "bi_tcxo_ao", |
| "sleep_clk", |
| "pcie_pipe_clk", |
| "usb3_phy_wrapper_gcc_usb30_pipe_clk"; |
| #power-domain-cells = <1>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| blsp1_uart3: serial@831000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x00831000 0x200>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| usb_hsphy: phy@ff4000 { |
| compatible = "qcom,sdx65-usb-hs-phy", |
| "qcom,usb-snps-hs-7nm-phy"; |
| reg = <0xff4000 0x120>; |
| #phy-cells = <0>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "ref"; |
| resets = <&gcc GCC_QUSB2PHY_BCR>; |
| status = "disabled"; |
| }; |
| |
| usb_qmpphy: phy@ff6000 { |
| compatible = "qcom,sdx65-qmp-usb3-uni-phy"; |
| reg = <0x00ff6000 0x2000>; |
| |
| clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, |
| <&gcc GCC_USB3_PRIM_CLKREF_EN>, |
| <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| <&gcc GCC_USB3_PHY_PIPE_CLK>; |
| clock-names = "aux", |
| "ref", |
| "cfg_ahb", |
| "pipe"; |
| clock-output-names = "usb3_uni_phy_pipe_clk_src"; |
| #clock-cells = <0>; |
| #phy-cells = <0>; |
| |
| resets = <&gcc GCC_USB3_PHY_BCR>, |
| <&gcc GCC_USB3PHY_PHY_BCR>; |
| reset-names = "phy", |
| "phy_phy"; |
| |
| status = "disabled"; |
| |
| }; |
| |
| system_noc: interconnect@1620000 { |
| compatible = "qcom,sdx65-system-noc"; |
| reg = <0x01620000 0x31200>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| qpic_bam: dma-controller@1b04000 { |
| compatible = "qcom,bam-v1.7.0"; |
| reg = <0x01b04000 0x1c000>; |
| interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&rpmhcc RPMH_QPIC_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| qcom,controlled-remotely; |
| status = "disabled"; |
| }; |
| |
| qpic_nand: nand-controller@1b30000 { |
| compatible = "qcom,sdx55-nand"; |
| reg = <0x01b30000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rpmhcc RPMH_QPIC_CLK>, |
| <&nand_clk_dummy>; |
| clock-names = "core", "aon"; |
| |
| dmas = <&qpic_bam 0>, |
| <&qpic_bam 1>, |
| <&qpic_bam 2>; |
| dma-names = "tx", "rx", "cmd"; |
| status = "disabled"; |
| }; |
| |
| pcie_ep: pcie-ep@1c00000 { |
| compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep"; |
| reg = <0x01c00000 0x3000>, |
| <0x40000000 0xf1d>, |
| <0x40000f20 0xa8>, |
| <0x40001000 0x1000>, |
| <0x40200000 0x100000>, |
| <0x01c03000 0x3000>; |
| reg-names = "parf", |
| "dbi", |
| "elbi", |
| "atu", |
| "addr_space", |
| "mmio"; |
| |
| qcom,perst-regs = <&tcsr 0xb258 0xb270>; |
| |
| clocks = <&gcc GCC_PCIE_AUX_CLK>, |
| <&gcc GCC_PCIE_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_MSTR_AXI_CLK>, |
| <&gcc GCC_PCIE_SLV_AXI_CLK>, |
| <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, |
| <&gcc GCC_PCIE_SLEEP_CLK>, |
| <&gcc GCC_PCIE_0_CLKREF_EN>; |
| clock-names = "aux", |
| "cfg", |
| "bus_master", |
| "bus_slave", |
| "slave_q2a", |
| "sleep", |
| "ref"; |
| |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "global", "doorbell"; |
| |
| resets = <&gcc GCC_PCIE_BCR>; |
| reset-names = "core"; |
| |
| power-domains = <&gcc PCIE_GDSC>; |
| |
| phys = <&pcie_phy>; |
| phy-names = "pciephy"; |
| |
| max-link-speed = <3>; |
| num-lanes = <2>; |
| |
| status = "disabled"; |
| }; |
| |
| pcie_phy: phy@1c06000 { |
| compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; |
| reg = <0x01c06000 0x2000>; |
| |
| clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, |
| <&gcc GCC_PCIE_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_0_CLKREF_EN>, |
| <&gcc GCC_PCIE_RCHNG_PHY_CLK>, |
| <&gcc GCC_PCIE_PIPE_CLK>; |
| clock-names = "aux", |
| "cfg_ahb", |
| "ref", |
| "rchng", |
| "pipe"; |
| |
| resets = <&gcc GCC_PCIE_PHY_BCR>; |
| reset-names = "phy"; |
| |
| assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; |
| assigned-clock-rates = <100000000>; |
| |
| power-domains = <&gcc PCIE_GDSC>; |
| |
| #clock-cells = <0>; |
| clock-output-names = "pcie_pipe_clk"; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| tcsr_mutex: hwlock@1f40000 { |
| compatible = "qcom,tcsr-mutex"; |
| reg = <0x01f40000 0x40000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| tcsr: syscon@1fcb000 { |
| compatible = "qcom,sdx65-tcsr", "syscon"; |
| reg = <0x01fc0000 0x1000>; |
| }; |
| |
| ipa: ipa@3f40000 { |
| compatible = "qcom,sdx65-ipa"; |
| |
| reg = <0x03f40000 0x10000>, |
| <0x03f50000 0x5000>, |
| <0x03e04000 0xfc000>; |
| reg-names = "ipa-reg", |
| "ipa-shared", |
| "gsi"; |
| |
| interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, |
| <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, |
| <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "ipa", |
| "gsi", |
| "ipa-clock-query", |
| "ipa-setup-ready"; |
| |
| iommus = <&apps_smmu 0x5e0 0x0>, |
| <&apps_smmu 0x5e2 0x0>; |
| |
| clocks = <&rpmhcc RPMH_IPA_CLK>; |
| clock-names = "core"; |
| |
| interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>, |
| <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>; |
| interconnect-names = "memory", |
| "config"; |
| |
| qcom,smem-states = <&ipa_smp2p_out 0>, |
| <&ipa_smp2p_out 1>; |
| qcom,smem-state-names = "ipa-clock-enabled-valid", |
| "ipa-clock-enabled"; |
| |
| status = "disabled"; |
| }; |
| |
| remoteproc_mpss: remoteproc@4080000 { |
| compatible = "qcom,sdx55-mpss-pas"; |
| reg = <0x04080000 0x4040>; |
| |
| interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", "fatal", "ready", "handover", |
| "stop-ack", "shutdown-ack"; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| |
| power-domains = <&rpmhpd SDX65_CX>, |
| <&rpmhpd SDX65_MSS>; |
| power-domain-names = "cx", "mss"; |
| |
| qcom,smem-states = <&modem_smp2p_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| status = "disabled"; |
| |
| glink-edge { |
| interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; |
| label = "mpss"; |
| qcom,remote-pid = <1>; |
| mboxes = <&apcs 15>; |
| }; |
| }; |
| |
| sdhc_1: mmc@8804000 { |
| compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; |
| reg = <0x08804000 0x1000>; |
| reg-names = "hc"; |
| interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| clocks = <&gcc GCC_SDCC1_AHB_CLK>, |
| <&gcc GCC_SDCC1_APPS_CLK>; |
| clock-names = "iface", "core"; |
| status = "disabled"; |
| }; |
| |
| mem_noc: interconnect@9680000 { |
| compatible = "qcom,sdx65-mem-noc"; |
| reg = <0x09680000 0x27200>; |
| #interconnect-cells = <1>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| usb: usb@a6f8800 { |
| compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; |
| reg = <0x0a6f8800 0x400>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, |
| <&gcc GCC_USB30_MASTER_CLK>, |
| <&gcc GCC_USB30_MSTR_AXI_CLK>, |
| <&gcc GCC_USB30_SLEEP_CLK>, |
| <&gcc GCC_USB30_MOCK_UTMI_CLK>; |
| clock-names = "cfg_noc", "core", "iface", "sleep", |
| "mock_utmi"; |
| |
| assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB30_MASTER_CLK>; |
| assigned-clock-rates = <19200000>, <200000000>; |
| |
| interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 19 IRQ_TYPE_EDGE_BOTH>, |
| <&pdc 18 IRQ_TYPE_EDGE_BOTH>, |
| <&pdc 76 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "pwr_event", |
| "hs_phy_irq", |
| "dp_hs_phy_irq", |
| "dm_hs_phy_irq", |
| "ss_phy_irq"; |
| |
| power-domains = <&gcc USB30_GDSC>; |
| |
| resets = <&gcc GCC_USB30_BCR>; |
| |
| status = "disabled"; |
| |
| usb_dwc3: usb@a600000 { |
| compatible = "snps,dwc3"; |
| reg = <0x0a600000 0xcd00>; |
| interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| iommus = <&apps_smmu 0x1a0 0x0>; |
| snps,dis_u2_susphy_quirk; |
| snps,dis_enblslpm_quirk; |
| phys = <&usb_hsphy>, <&usb_qmpphy>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| }; |
| }; |
| |
| restart@c264000 { |
| compatible = "qcom,pshold"; |
| reg = <0x0c264000 0x1000>; |
| }; |
| |
| spmi_bus: spmi@c440000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0xc440000 0xd00>, |
| <0xc600000 0x2000000>, |
| <0xe600000 0x100000>, |
| <0xe700000 0xa0000>, |
| <0xc40a000 0x26000>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "periph_irq"; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| qcom,channel = <0>; |
| qcom,ee = <0>; |
| }; |
| |
| tlmm: pinctrl@f100000 { |
| compatible = "qcom,sdx65-tlmm"; |
| reg = <0xf100000 0x300000>; |
| interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&tlmm 0 0 109>; |
| interrupt-controller; |
| interrupt-parent = <&intc>; |
| #interrupt-cells = <2>; |
| }; |
| |
| pdc: interrupt-controller@b210000 { |
| compatible = "qcom,sdx65-pdc", "qcom,pdc"; |
| reg = <0xb210000 0x10000>; |
| qcom,pdc-ranges = <0 147 52>, <52 266 32>; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&intc>; |
| interrupt-controller; |
| }; |
| |
| sram@1468f000 { |
| compatible = "qcom,sdx65-imem", "syscon", "simple-mfd"; |
| reg = <0x1468f000 0x1000>; |
| ranges = <0x0 0x1468f000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| pil-reloc@94c { |
| compatible = "qcom,pil-reloc-info"; |
| reg = <0x94c 0xc8>; |
| }; |
| }; |
| |
| apps_smmu: iommu@15000000 { |
| compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500"; |
| reg = <0x15000000 0x40000>; |
| #iommu-cells = <2>; |
| #global-interrupts = <1>; |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| intc: interrupt-controller@17800000 { |
| compatible = "qcom,msm-qgic2"; |
| interrupt-controller; |
| interrupt-parent = <&intc>; |
| #interrupt-cells = <3>; |
| reg = <0x17800000 0x1000>, |
| <0x17802000 0x1000>; |
| }; |
| |
| a7pll: clock@17808000 { |
| compatible = "qcom,sdx55-a7pll"; |
| reg = <0x17808000 0x1000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "bi_tcxo"; |
| #clock-cells = <0>; |
| }; |
| |
| apcs: mailbox@17810000 { |
| compatible = "qcom,sdx55-apcs-gcc", "syscon"; |
| reg = <0x17810000 0x2000>; |
| #mbox-cells = <1>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; |
| clock-names = "ref", "pll", "aux"; |
| #clock-cells = <0>; |
| }; |
| |
| watchdog@17817000 { |
| compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt"; |
| reg = <0x17817000 0x1000>; |
| clocks = <&sleep_clk>; |
| }; |
| |
| timer@17820000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x17820000 0x1000>; |
| clock-frequency = <19200000>; |
| |
| frame@17821000 { |
| frame-number = <0>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17821000 0x1000>, |
| <0x17822000 0x1000>; |
| }; |
| |
| frame@17823000 { |
| frame-number = <1>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17823000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17824000 { |
| frame-number = <2>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17824000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17825000 { |
| frame-number = <3>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17825000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17826000 { |
| frame-number = <4>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17826000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17827000 { |
| frame-number = <5>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17827000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17828000 { |
| frame-number = <6>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17828000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17829000 { |
| frame-number = <7>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17829000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| apps_rsc: rsc@17830000 { |
| label = "apps_rsc"; |
| compatible = "qcom,rpmh-rsc"; |
| reg = <0x17830000 0x10000>, |
| <0x17840000 0x10000>; |
| reg-names = "drv-0", "drv-1"; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,tcs-offset = <0xd00>; |
| qcom,drv-id = <1>; |
| qcom,tcs-config = <ACTIVE_TCS 2>, |
| <SLEEP_TCS 2>, |
| <WAKE_TCS 2>, |
| <CONTROL_TCS 1>; |
| |
| rpmhcc: clock-controller { |
| compatible = "qcom,sdx65-rpmh-clk"; |
| #clock-cells = <1>; |
| clock-names = "xo"; |
| clocks = <&xo_board>; |
| }; |
| |
| rpmhpd: power-controller { |
| compatible = "qcom,sdx65-rpmhpd"; |
| #power-domain-cells = <1>; |
| operating-points-v2 = <&rpmhpd_opp_table>; |
| |
| rpmhpd_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| rpmhpd_opp_ret: opp1 { |
| opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
| }; |
| |
| rpmhpd_opp_min_svs: opp2 { |
| opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; |
| }; |
| |
| rpmhpd_opp_low_svs: opp3 { |
| opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
| }; |
| |
| rpmhpd_opp_svs: opp4 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
| }; |
| |
| rpmhpd_opp_svs_l1: opp5 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| }; |
| |
| rpmhpd_opp_nom: opp6 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
| }; |
| |
| rpmhpd_opp_nom_l1: opp7 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| }; |
| |
| rpmhpd_opp_nom_l2: opp8 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; |
| }; |
| |
| rpmhpd_opp_turbo: opp9 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; |
| }; |
| |
| rpmhpd_opp_turbo_l1: opp10 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; |
| }; |
| }; |
| }; |
| |
| apps_bcm_voter: bcm-voter { |
| compatible = "qcom,bcm-voter"; |
| }; |
| |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| clock-frequency = <19200000>; |
| }; |
| }; |
