| /* | |
| * Device Tree Source for the r8a7743 SoC | |
| * | |
| * Copyright (C) 2016-2017 Cogent Embedded Inc. | |
| * | |
| * This file is licensed under the terms of the GNU General Public License | |
| * version 2. This program is licensed "as is" without any warranty of any | |
| * kind, whether express or implied. | |
| */ | |
| #include <dt-bindings/interrupt-controller/irq.h> | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| #include <dt-bindings/clock/r8a7743-cpg-mssr.h> | |
| #include <dt-bindings/power/r8a7743-sysc.h> | |
| / { | |
| compatible = "renesas,r8a7743"; | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| aliases { | |
| i2c0 = &i2c0; | |
| i2c1 = &i2c1; | |
| i2c2 = &i2c2; | |
| i2c3 = &i2c3; | |
| i2c4 = &i2c4; | |
| i2c5 = &i2c5; | |
| }; | |
| cpus { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| enable-method = "renesas,apmu"; | |
| cpu0: cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a15"; | |
| reg = <0>; | |
| clock-frequency = <1500000000>; | |
| clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; | |
| clock-latency = <300000>; /* 300 us */ | |
| power-domains = <&sysc R8A7743_PD_CA15_CPU0>; | |
| next-level-cache = <&L2_CA15>; | |
| /* kHz - uV - OPPs unknown yet */ | |
| operating-points = <1500000 1000000>, | |
| <1312500 1000000>, | |
| <1125000 1000000>, | |
| < 937500 1000000>, | |
| < 750000 1000000>, | |
| < 375000 1000000>; | |
| }; | |
| cpu1: cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a15"; | |
| reg = <1>; | |
| clock-frequency = <1500000000>; | |
| power-domains = <&sysc R8A7743_PD_CA15_CPU1>; | |
| next-level-cache = <&L2_CA15>; | |
| }; | |
| L2_CA15: cache-controller-0 { | |
| compatible = "cache"; | |
| cache-unified; | |
| cache-level = <2>; | |
| power-domains = <&sysc R8A7743_PD_CA15_SCU>; | |
| }; | |
| }; | |
| soc { | |
| compatible = "simple-bus"; | |
| interrupt-parent = <&gic>; | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| ranges; | |
| apmu@e6152000 { | |
| compatible = "renesas,r8a7743-apmu", "renesas,apmu"; | |
| reg = <0 0xe6152000 0 0x188>; | |
| cpus = <&cpu0 &cpu1>; | |
| }; | |
| gic: interrupt-controller@f1001000 { | |
| compatible = "arm,gic-400"; | |
| #interrupt-cells = <3>; | |
| #address-cells = <0>; | |
| interrupt-controller; | |
| reg = <0 0xf1001000 0 0x1000>, | |
| <0 0xf1002000 0 0x2000>, | |
| <0 0xf1004000 0 0x2000>, | |
| <0 0xf1006000 0 0x2000>; | |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | | |
| IRQ_TYPE_LEVEL_HIGH)>; | |
| clocks = <&cpg CPG_MOD 408>; | |
| clock-names = "clk"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 408>; | |
| }; | |
| gpio0: gpio@e6050000 { | |
| compatible = "renesas,gpio-r8a7743", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6050000 0 0x50>; | |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 0 32>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 912>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 912>; | |
| }; | |
| gpio1: gpio@e6051000 { | |
| compatible = "renesas,gpio-r8a7743", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6051000 0 0x50>; | |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 32 26>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 911>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 911>; | |
| }; | |
| gpio2: gpio@e6052000 { | |
| compatible = "renesas,gpio-r8a7743", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6052000 0 0x50>; | |
| interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 64 32>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 910>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 910>; | |
| }; | |
| gpio3: gpio@e6053000 { | |
| compatible = "renesas,gpio-r8a7743", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6053000 0 0x50>; | |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 96 32>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 909>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 909>; | |
| }; | |
| gpio4: gpio@e6054000 { | |
| compatible = "renesas,gpio-r8a7743", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6054000 0 0x50>; | |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 128 32>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 908>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 908>; | |
| }; | |
| gpio5: gpio@e6055000 { | |
| compatible = "renesas,gpio-r8a7743", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6055000 0 0x50>; | |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 160 32>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 907>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 907>; | |
| }; | |
| gpio6: gpio@e6055400 { | |
| compatible = "renesas,gpio-r8a7743", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6055400 0 0x50>; | |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 192 32>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 905>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 905>; | |
| }; | |
| gpio7: gpio@e6055800 { | |
| compatible = "renesas,gpio-r8a7743", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6055800 0 0x50>; | |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 224 26>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 904>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 904>; | |
| }; | |
| irqc: interrupt-controller@e61c0000 { | |
| compatible = "renesas,irqc-r8a7743", "renesas,irqc"; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| reg = <0 0xe61c0000 0 0x200>; | |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 407>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 407>; | |
| }; | |
| timer { | |
| compatible = "arm,armv7-timer"; | |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | | |
| IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | | |
| IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | | |
| IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | | |
| IRQ_TYPE_LEVEL_LOW)>; | |
| }; | |
| cpg: clock-controller@e6150000 { | |
| compatible = "renesas,r8a7743-cpg-mssr"; | |
| reg = <0 0xe6150000 0 0x1000>; | |
| clocks = <&extal_clk>, <&usb_extal_clk>; | |
| clock-names = "extal", "usb_extal"; | |
| #clock-cells = <2>; | |
| #power-domain-cells = <0>; | |
| #reset-cells = <1>; | |
| }; | |
| prr: chipid@ff000044 { | |
| compatible = "renesas,prr"; | |
| reg = <0 0xff000044 0 4>; | |
| }; | |
| rst: reset-controller@e6160000 { | |
| compatible = "renesas,r8a7743-rst"; | |
| reg = <0 0xe6160000 0 0x100>; | |
| }; | |
| sysc: system-controller@e6180000 { | |
| compatible = "renesas,r8a7743-sysc"; | |
| reg = <0 0xe6180000 0 0x200>; | |
| #power-domain-cells = <1>; | |
| }; | |
| pfc: pin-controller@e6060000 { | |
| compatible = "renesas,pfc-r8a7743"; | |
| reg = <0 0xe6060000 0 0x250>; | |
| }; | |
| dmac0: dma-controller@e6700000 { | |
| compatible = "renesas,dmac-r8a7743", | |
| "renesas,rcar-dmac"; | |
| reg = <0 0xe6700000 0 0x20000>; | |
| interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-names = "error", | |
| "ch0", "ch1", "ch2", "ch3", | |
| "ch4", "ch5", "ch6", "ch7", | |
| "ch8", "ch9", "ch10", "ch11", | |
| "ch12", "ch13", "ch14"; | |
| clocks = <&cpg CPG_MOD 219>; | |
| clock-names = "fck"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 219>; | |
| #dma-cells = <1>; | |
| dma-channels = <15>; | |
| }; | |
| dmac1: dma-controller@e6720000 { | |
| compatible = "renesas,dmac-r8a7743", | |
| "renesas,rcar-dmac"; | |
| reg = <0 0xe6720000 0 0x20000>; | |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-names = "error", | |
| "ch0", "ch1", "ch2", "ch3", | |
| "ch4", "ch5", "ch6", "ch7", | |
| "ch8", "ch9", "ch10", "ch11", | |
| "ch12", "ch13", "ch14"; | |
| clocks = <&cpg CPG_MOD 218>; | |
| clock-names = "fck"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 218>; | |
| #dma-cells = <1>; | |
| dma-channels = <15>; | |
| }; | |
| /* The memory map in the User's Manual maps the cores to bus | |
| * numbers | |
| */ | |
| i2c0: i2c@e6508000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "renesas,i2c-r8a7743", | |
| "renesas,rcar-gen2-i2c"; | |
| reg = <0 0xe6508000 0 0x40>; | |
| interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 931>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 931>; | |
| i2c-scl-internal-delay-ns = <6>; | |
| status = "disabled"; | |
| }; | |
| i2c1: i2c@e6518000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "renesas,i2c-r8a7743", | |
| "renesas,rcar-gen2-i2c"; | |
| reg = <0 0xe6518000 0 0x40>; | |
| interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 930>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 930>; | |
| i2c-scl-internal-delay-ns = <6>; | |
| status = "disabled"; | |
| }; | |
| i2c2: i2c@e6530000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "renesas,i2c-r8a7743", | |
| "renesas,rcar-gen2-i2c"; | |
| reg = <0 0xe6530000 0 0x40>; | |
| interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 929>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 929>; | |
| i2c-scl-internal-delay-ns = <6>; | |
| status = "disabled"; | |
| }; | |
| i2c3: i2c@e6540000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "renesas,i2c-r8a7743", | |
| "renesas,rcar-gen2-i2c"; | |
| reg = <0 0xe6540000 0 0x40>; | |
| interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 928>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 928>; | |
| i2c-scl-internal-delay-ns = <6>; | |
| status = "disabled"; | |
| }; | |
| i2c4: i2c@e6520000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "renesas,i2c-r8a7743", | |
| "renesas,rcar-gen2-i2c"; | |
| reg = <0 0xe6520000 0 0x40>; | |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 927>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 927>; | |
| i2c-scl-internal-delay-ns = <6>; | |
| status = "disabled"; | |
| }; | |
| i2c5: i2c@e6528000 { | |
| /* doesn't need pinmux */ | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "renesas,i2c-r8a7743", | |
| "renesas,rcar-gen2-i2c"; | |
| reg = <0 0xe6528000 0 0x40>; | |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 925>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 925>; | |
| i2c-scl-internal-delay-ns = <110>; | |
| status = "disabled"; | |
| }; | |
| scifa0: serial@e6c40000 { | |
| compatible = "renesas,scifa-r8a7743", | |
| "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
| reg = <0 0xe6c40000 0 0x40>; | |
| interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 204>; | |
| clock-names = "fck"; | |
| dmas = <&dmac0 0x21>, <&dmac0 0x22>, | |
| <&dmac1 0x21>, <&dmac1 0x22>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 204>; | |
| status = "disabled"; | |
| }; | |
| scifa1: serial@e6c50000 { | |
| compatible = "renesas,scifa-r8a7743", | |
| "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
| reg = <0 0xe6c50000 0 0x40>; | |
| interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 203>; | |
| clock-names = "fck"; | |
| dmas = <&dmac0 0x25>, <&dmac0 0x26>, | |
| <&dmac1 0x25>, <&dmac1 0x26>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 203>; | |
| status = "disabled"; | |
| }; | |
| scifa2: serial@e6c60000 { | |
| compatible = "renesas,scifa-r8a7743", | |
| "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
| reg = <0 0xe6c60000 0 0x40>; | |
| interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 202>; | |
| clock-names = "fck"; | |
| dmas = <&dmac0 0x27>, <&dmac0 0x28>, | |
| <&dmac1 0x27>, <&dmac1 0x28>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 202>; | |
| status = "disabled"; | |
| }; | |
| scifa3: serial@e6c70000 { | |
| compatible = "renesas,scifa-r8a7743", | |
| "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
| reg = <0 0xe6c70000 0 0x40>; | |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 1106>; | |
| clock-names = "fck"; | |
| dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, | |
| <&dmac1 0x1b>, <&dmac1 0x1c>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 1106>; | |
| status = "disabled"; | |
| }; | |
| scifa4: serial@e6c78000 { | |
| compatible = "renesas,scifa-r8a7743", | |
| "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
| reg = <0 0xe6c78000 0 0x40>; | |
| interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 1107>; | |
| clock-names = "fck"; | |
| dmas = <&dmac0 0x1f>, <&dmac0 0x20>, | |
| <&dmac1 0x1f>, <&dmac1 0x20>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 1107>; | |
| status = "disabled"; | |
| }; | |
| scifa5: serial@e6c80000 { | |
| compatible = "renesas,scifa-r8a7743", | |
| "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
| reg = <0 0xe6c80000 0 0x40>; | |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 1108>; | |
| clock-names = "fck"; | |
| dmas = <&dmac0 0x23>, <&dmac0 0x24>, | |
| <&dmac1 0x23>, <&dmac1 0x24>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 1108>; | |
| status = "disabled"; | |
| }; | |
| scifb0: serial@e6c20000 { | |
| compatible = "renesas,scifb-r8a7743", | |
| "renesas,rcar-gen2-scifb", "renesas,scifb"; | |
| reg = <0 0xe6c20000 0 0x100>; | |
| interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 206>; | |
| clock-names = "fck"; | |
| dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, | |
| <&dmac1 0x3d>, <&dmac1 0x3e>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 206>; | |
| status = "disabled"; | |
| }; | |
| scifb1: serial@e6c30000 { | |
| compatible = "renesas,scifb-r8a7743", | |
| "renesas,rcar-gen2-scifb", "renesas,scifb"; | |
| reg = <0 0xe6c30000 0 0x100>; | |
| interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 207>; | |
| clock-names = "fck"; | |
| dmas = <&dmac0 0x19>, <&dmac0 0x1a>, | |
| <&dmac1 0x19>, <&dmac1 0x1a>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 207>; | |
| status = "disabled"; | |
| }; | |
| scifb2: serial@e6ce0000 { | |
| compatible = "renesas,scifb-r8a7743", | |
| "renesas,rcar-gen2-scifb", "renesas,scifb"; | |
| reg = <0 0xe6ce0000 0 0x100>; | |
| interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 216>; | |
| clock-names = "fck"; | |
| dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, | |
| <&dmac1 0x1d>, <&dmac1 0x1e>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 216>; | |
| status = "disabled"; | |
| }; | |
| scif0: serial@e6e60000 { | |
| compatible = "renesas,scif-r8a7743", | |
| "renesas,rcar-gen2-scif", "renesas,scif"; | |
| reg = <0 0xe6e60000 0 0x40>; | |
| interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 721>, | |
| <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; | |
| clock-names = "fck", "brg_int", "scif_clk"; | |
| dmas = <&dmac0 0x29>, <&dmac0 0x2a>, | |
| <&dmac1 0x29>, <&dmac1 0x2a>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 721>; | |
| status = "disabled"; | |
| }; | |
| scif1: serial@e6e68000 { | |
| compatible = "renesas,scif-r8a7743", | |
| "renesas,rcar-gen2-scif", "renesas,scif"; | |
| reg = <0 0xe6e68000 0 0x40>; | |
| interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 720>, | |
| <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; | |
| clock-names = "fck", "brg_int", "scif_clk"; | |
| dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, | |
| <&dmac1 0x2d>, <&dmac1 0x2e>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 720>; | |
| status = "disabled"; | |
| }; | |
| scif2: serial@e6e58000 { | |
| compatible = "renesas,scif-r8a7743", | |
| "renesas,rcar-gen2-scif", "renesas,scif"; | |
| reg = <0 0xe6e58000 0 0x40>; | |
| interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 719>, | |
| <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; | |
| clock-names = "fck", "brg_int", "scif_clk"; | |
| dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, | |
| <&dmac1 0x2b>, <&dmac1 0x2c>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 719>; | |
| status = "disabled"; | |
| }; | |
| scif3: serial@e6ea8000 { | |
| compatible = "renesas,scif-r8a7743", | |
| "renesas,rcar-gen2-scif", "renesas,scif"; | |
| reg = <0 0xe6ea8000 0 0x40>; | |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 718>, | |
| <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; | |
| clock-names = "fck", "brg_int", "scif_clk"; | |
| dmas = <&dmac0 0x2f>, <&dmac0 0x30>, | |
| <&dmac1 0x2f>, <&dmac1 0x30>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 718>; | |
| status = "disabled"; | |
| }; | |
| scif4: serial@e6ee0000 { | |
| compatible = "renesas,scif-r8a7743", | |
| "renesas,rcar-gen2-scif", "renesas,scif"; | |
| reg = <0 0xe6ee0000 0 0x40>; | |
| interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 715>, | |
| <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; | |
| clock-names = "fck", "brg_int", "scif_clk"; | |
| dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, | |
| <&dmac1 0xfb>, <&dmac1 0xfc>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 715>; | |
| status = "disabled"; | |
| }; | |
| scif5: serial@e6ee8000 { | |
| compatible = "renesas,scif-r8a7743", | |
| "renesas,rcar-gen2-scif", "renesas,scif"; | |
| reg = <0 0xe6ee8000 0 0x40>; | |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 714>, | |
| <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; | |
| clock-names = "fck", "brg_int", "scif_clk"; | |
| dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, | |
| <&dmac1 0xfd>, <&dmac1 0xfe>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 714>; | |
| status = "disabled"; | |
| }; | |
| hscif0: serial@e62c0000 { | |
| compatible = "renesas,hscif-r8a7743", | |
| "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
| reg = <0 0xe62c0000 0 0x60>; | |
| interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 717>, | |
| <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; | |
| clock-names = "fck", "brg_int", "scif_clk"; | |
| dmas = <&dmac0 0x39>, <&dmac0 0x3a>, | |
| <&dmac1 0x39>, <&dmac1 0x3a>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 717>; | |
| status = "disabled"; | |
| }; | |
| hscif1: serial@e62c8000 { | |
| compatible = "renesas,hscif-r8a7743", | |
| "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
| reg = <0 0xe62c8000 0 0x60>; | |
| interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 716>, | |
| <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; | |
| clock-names = "fck", "brg_int", "scif_clk"; | |
| dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, | |
| <&dmac1 0x4d>, <&dmac1 0x4e>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 716>; | |
| status = "disabled"; | |
| }; | |
| hscif2: serial@e62d0000 { | |
| compatible = "renesas,hscif-r8a7743", | |
| "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
| reg = <0 0xe62d0000 0 0x60>; | |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 713>, | |
| <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; | |
| clock-names = "fck", "brg_int", "scif_clk"; | |
| dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, | |
| <&dmac1 0x3b>, <&dmac1 0x3c>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 713>; | |
| status = "disabled"; | |
| }; | |
| icram2: sram@e6300000 { | |
| compatible = "mmio-sram"; | |
| reg = <0 0xe6300000 0 0x40000>; | |
| }; | |
| icram0: sram@e63a0000 { | |
| compatible = "mmio-sram"; | |
| reg = <0 0xe63a0000 0 0x12000>; | |
| }; | |
| icram1: sram@e63c0000 { | |
| compatible = "mmio-sram"; | |
| reg = <0 0xe63c0000 0 0x1000>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges = <0 0 0xe63c0000 0x1000>; | |
| smp-sram@0 { | |
| compatible = "renesas,smp-sram"; | |
| reg = <0 0x10>; | |
| }; | |
| }; | |
| ether: ethernet@ee700000 { | |
| compatible = "renesas,ether-r8a7743"; | |
| reg = <0 0xee700000 0 0x400>; | |
| interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 813>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 813>; | |
| phy-mode = "rmii"; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| status = "disabled"; | |
| }; | |
| avb: ethernet@e6800000 { | |
| compatible = "renesas,etheravb-r8a7743", | |
| "renesas,etheravb-rcar-gen2"; | |
| reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; | |
| interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 812>; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 812>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| status = "disabled"; | |
| }; | |
| mmcif0: mmc@ee200000 { | |
| compatible = "renesas,mmcif-r8a7743", | |
| "renesas,sh-mmcif"; | |
| reg = <0 0xee200000 0 0x80>; | |
| interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 315>; | |
| dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, | |
| <&dmac1 0xd1>, <&dmac1 0xd2>; | |
| dma-names = "tx", "rx", "tx", "rx"; | |
| power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; | |
| resets = <&cpg 315>; | |
| reg-io-width = <4>; | |
| max-frequency = <97500000>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| /* External root clock */ | |
| extal_clk: extal { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| /* This value must be overridden by the board. */ | |
| clock-frequency = <0>; | |
| }; | |
| /* External USB clock - can be overridden by the board */ | |
| usb_extal_clk: usb_extal { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <48000000>; | |
| }; | |
| /* External SCIF clock */ | |
| scif_clk: scif { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| /* This value must be overridden by the board. */ | |
| clock-frequency = <0>; | |
| }; | |
| }; |