| // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| /* |
| * Device Tree Source for the RZ/G3S SoC |
| * |
| * Copyright (C) 2023 Renesas Electronics Corp. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/r9a08g045-cpg.h> |
| |
| / { |
| compatible = "renesas,r9a08g045"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a55"; |
| reg = <0>; |
| device_type = "cpu"; |
| #cooling-cells = <2>; |
| next-level-cache = <&L3_CA55>; |
| enable-method = "psci"; |
| clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; |
| }; |
| |
| L3_CA55: cache-controller-0 { |
| compatible = "cache"; |
| cache-level = <3>; |
| cache-unified; |
| cache-size = <0x40000>; |
| }; |
| }; |
| |
| extal_clk: extal-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board. */ |
| clock-frequency = <0>; |
| }; |
| |
| soc: soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| scif0: serial@1004b800 { |
| compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; |
| reg = <0 0x1004b800 0 0x400>; |
| interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "eri", "rxi", "txi", |
| "bri", "dri", "tei"; |
| clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; |
| clock-names = "fck"; |
| power-domains = <&cpg>; |
| resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; |
| status = "disabled"; |
| }; |
| |
| cpg: clock-controller@11010000 { |
| compatible = "renesas,r9a08g045-cpg"; |
| reg = <0 0x11010000 0 0x10000>; |
| clocks = <&extal_clk>; |
| clock-names = "extal"; |
| #clock-cells = <2>; |
| #reset-cells = <1>; |
| #power-domain-cells = <0>; |
| }; |
| |
| sysc: system-controller@11020000 { |
| compatible = "renesas,r9a08g045-sysc"; |
| reg = <0 0x11020000 0 0x10000>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "lpm_int", "ca55stbydone_int", |
| "cm33stbyr_int", "ca55_deny"; |
| status = "disabled"; |
| }; |
| |
| pinctrl: pinctrl@11030000 { |
| compatible = "renesas,r9a08g045-pinctrl"; |
| reg = <0 0x11030000 0 0x10000>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&pinctrl 0 0 152>; |
| clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; |
| power-domains = <&cpg>; |
| resets = <&cpg R9A08G045_GPIO_RSTN>, |
| <&cpg R9A08G045_GPIO_PORT_RESETN>, |
| <&cpg R9A08G045_GPIO_SPARE_RESETN>; |
| }; |
| |
| sdhi0: mmc@11c00000 { |
| compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; |
| reg = <0x0 0x11c00000 0 0x10000>; |
| interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, |
| <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, |
| <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, |
| <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; |
| clock-names = "core", "clkh", "cd", "aclk"; |
| resets = <&cpg R9A08G045_SDHI0_IXRST>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| sdhi1: mmc@11c10000 { |
| compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; |
| reg = <0x0 0x11c10000 0 0x10000>; |
| interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, |
| <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, |
| <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, |
| <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; |
| clock-names = "core", "clkh", "cd", "aclk"; |
| resets = <&cpg R9A08G045_SDHI1_IXRST>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| sdhi2: mmc@11c20000 { |
| compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; |
| reg = <0x0 0x11c20000 0 0x10000>; |
| interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, |
| <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, |
| <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, |
| <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; |
| clock-names = "core", "clkh", "cd", "aclk"; |
| resets = <&cpg R9A08G045_SDHI2_IXRST>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@12400000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x0 0x12400000 0 0x40000>, |
| <0x0 0x12440000 0 0x60000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| }; |