| /* |
| * Copyright (C) 2016 ARM Ltd. |
| * based on the Allwinner H3 dtsi: |
| * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> |
| * |
| * This file is dual-licensed: you can use it either under the terms |
| * of the GPL or the X11 license, at your option. Note that this dual |
| * licensing only applies to this file, and not this project as a |
| * whole. |
| * |
| * a) This file is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of the |
| * License, or (at your option) any later version. |
| * |
| * This file is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * Or, alternatively, |
| * |
| * b) Permission is hereby granted, free of charge, to any person |
| * obtaining a copy of this software and associated documentation |
| * files (the "Software"), to deal in the Software without |
| * restriction, including without limitation the rights to use, |
| * copy, modify, merge, publish, distribute, sublicense, and/or |
| * sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following |
| * conditions: |
| * |
| * The above copyright notice and this permission notice shall be |
| * included in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| #include <dt-bindings/clock/sun50i-a64-ccu.h> |
| #include <dt-bindings/clock/sun8i-r-ccu.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/reset/sun50i-a64-ccu.h> |
| |
| / { |
| interrupt-parent = <&gic>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| chosen { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| /* |
| * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU. |
| * However there is no support for this clock on A64 yet, so we depend |
| * on the upstream clocks here to keep them (and thus CLK_MIXER0) up. |
| */ |
| simplefb_lcd: framebuffer-lcd { |
| compatible = "allwinner,simple-framebuffer", |
| "simple-framebuffer"; |
| allwinner,pipeline = "mixer0-lcd0"; |
| clocks = <&ccu CLK_TCON0>, |
| <&ccu CLK_DE>, <&ccu CLK_BUS_DE>; |
| status = "disabled"; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0>; |
| enable-method = "psci"; |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <1>; |
| enable-method = "psci"; |
| }; |
| |
| cpu2: cpu@2 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <2>; |
| enable-method = "psci"; |
| }; |
| |
| cpu3: cpu@3 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <3>; |
| enable-method = "psci"; |
| }; |
| }; |
| |
| osc24M: osc24M_clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| clock-output-names = "osc24M"; |
| }; |
| |
| osc32k: osc32k_clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <32768>; |
| clock-output-names = "osc32k"; |
| }; |
| |
| iosc: internal-osc-clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <16000000>; |
| clock-accuracy = <300000000>; |
| clock-output-names = "iosc"; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| sound_spdif { |
| compatible = "simple-audio-card"; |
| simple-audio-card,name = "On-board SPDIF"; |
| |
| simple-audio-card,cpu { |
| sound-dai = <&spdif>; |
| }; |
| |
| simple-audio-card,codec { |
| sound-dai = <&spdif_out>; |
| }; |
| }; |
| |
| spdif_out: spdif-out { |
| #sound-dai-cells = <0>; |
| compatible = "linux,spdif-dit"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| syscon: syscon@1c00000 { |
| compatible = "allwinner,sun50i-a64-system-controller", |
| "syscon"; |
| reg = <0x01c00000 0x1000>; |
| }; |
| |
| dma: dma-controller@1c02000 { |
| compatible = "allwinner,sun50i-a64-dma"; |
| reg = <0x01c02000 0x1000>; |
| interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_DMA>; |
| dma-channels = <8>; |
| dma-requests = <27>; |
| resets = <&ccu RST_BUS_DMA>; |
| #dma-cells = <1>; |
| }; |
| |
| mmc0: mmc@1c0f000 { |
| compatible = "allwinner,sun50i-a64-mmc"; |
| reg = <0x01c0f000 0x1000>; |
| clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; |
| clock-names = "ahb", "mmc"; |
| resets = <&ccu RST_BUS_MMC0>; |
| reset-names = "ahb"; |
| interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| max-frequency = <150000000>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| mmc1: mmc@1c10000 { |
| compatible = "allwinner,sun50i-a64-mmc"; |
| reg = <0x01c10000 0x1000>; |
| clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; |
| clock-names = "ahb", "mmc"; |
| resets = <&ccu RST_BUS_MMC1>; |
| reset-names = "ahb"; |
| interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| max-frequency = <150000000>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| mmc2: mmc@1c11000 { |
| compatible = "allwinner,sun50i-a64-emmc"; |
| reg = <0x01c11000 0x1000>; |
| clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; |
| clock-names = "ahb", "mmc"; |
| resets = <&ccu RST_BUS_MMC2>; |
| reset-names = "ahb"; |
| interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| max-frequency = <200000000>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| usb_otg: usb@1c19000 { |
| compatible = "allwinner,sun8i-a33-musb"; |
| reg = <0x01c19000 0x0400>; |
| clocks = <&ccu CLK_BUS_OTG>; |
| resets = <&ccu RST_BUS_OTG>; |
| interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "mc"; |
| phys = <&usbphy 0>; |
| phy-names = "usb"; |
| extcon = <&usbphy 0>; |
| status = "disabled"; |
| }; |
| |
| usbphy: phy@1c19400 { |
| compatible = "allwinner,sun50i-a64-usb-phy"; |
| reg = <0x01c19400 0x14>, |
| <0x01c1a800 0x4>, |
| <0x01c1b800 0x4>; |
| reg-names = "phy_ctrl", |
| "pmu0", |
| "pmu1"; |
| clocks = <&ccu CLK_USB_PHY0>, |
| <&ccu CLK_USB_PHY1>; |
| clock-names = "usb0_phy", |
| "usb1_phy"; |
| resets = <&ccu RST_USB_PHY0>, |
| <&ccu RST_USB_PHY1>; |
| reset-names = "usb0_reset", |
| "usb1_reset"; |
| status = "disabled"; |
| #phy-cells = <1>; |
| }; |
| |
| ehci0: usb@1c1a000 { |
| compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; |
| reg = <0x01c1a000 0x100>; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI0>, |
| <&ccu CLK_BUS_EHCI0>, |
| <&ccu CLK_USB_OHCI0>; |
| resets = <&ccu RST_BUS_OHCI0>, |
| <&ccu RST_BUS_EHCI0>; |
| status = "disabled"; |
| }; |
| |
| ohci0: usb@1c1a400 { |
| compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; |
| reg = <0x01c1a400 0x100>; |
| interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI0>, |
| <&ccu CLK_USB_OHCI0>; |
| resets = <&ccu RST_BUS_OHCI0>; |
| status = "disabled"; |
| }; |
| |
| ehci1: usb@1c1b000 { |
| compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; |
| reg = <0x01c1b000 0x100>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI1>, |
| <&ccu CLK_BUS_EHCI1>, |
| <&ccu CLK_USB_OHCI1>; |
| resets = <&ccu RST_BUS_OHCI1>, |
| <&ccu RST_BUS_EHCI1>; |
| phys = <&usbphy 1>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ohci1: usb@1c1b400 { |
| compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; |
| reg = <0x01c1b400 0x100>; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI1>, |
| <&ccu CLK_USB_OHCI1>; |
| resets = <&ccu RST_BUS_OHCI1>; |
| phys = <&usbphy 1>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ccu: clock@1c20000 { |
| compatible = "allwinner,sun50i-a64-ccu"; |
| reg = <0x01c20000 0x400>; |
| clocks = <&osc24M>, <&osc32k>; |
| clock-names = "hosc", "losc"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| pio: pinctrl@1c20800 { |
| compatible = "allwinner,sun50i-a64-pinctrl"; |
| reg = <0x01c20800 0x400>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu 58>; |
| gpio-controller; |
| #gpio-cells = <3>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| |
| i2c0_pins: i2c0_pins { |
| pins = "PH0", "PH1"; |
| function = "i2c0"; |
| }; |
| |
| i2c1_pins: i2c1_pins { |
| pins = "PH2", "PH3"; |
| function = "i2c1"; |
| }; |
| |
| mmc0_pins: mmc0-pins { |
| pins = "PF0", "PF1", "PF2", "PF3", |
| "PF4", "PF5"; |
| function = "mmc0"; |
| drive-strength = <30>; |
| bias-pull-up; |
| }; |
| |
| mmc1_pins: mmc1-pins { |
| pins = "PG0", "PG1", "PG2", "PG3", |
| "PG4", "PG5"; |
| function = "mmc1"; |
| drive-strength = <30>; |
| bias-pull-up; |
| }; |
| |
| mmc2_pins: mmc2-pins { |
| pins = "PC1", "PC5", "PC6", "PC8", "PC9", |
| "PC10","PC11", "PC12", "PC13", |
| "PC14", "PC15", "PC16"; |
| function = "mmc2"; |
| drive-strength = <30>; |
| bias-pull-up; |
| }; |
| |
| rmii_pins: rmii_pins { |
| pins = "PD10", "PD11", "PD13", "PD14", "PD17", |
| "PD18", "PD19", "PD20", "PD22", "PD23"; |
| function = "emac"; |
| drive-strength = <40>; |
| }; |
| |
| rgmii_pins: rgmii_pins { |
| pins = "PD8", "PD9", "PD10", "PD11", "PD12", |
| "PD13", "PD15", "PD16", "PD17", "PD18", |
| "PD19", "PD20", "PD21", "PD22", "PD23"; |
| function = "emac"; |
| drive-strength = <40>; |
| }; |
| |
| spdif_tx_pin: spdif { |
| pins = "PH8"; |
| function = "spdif"; |
| }; |
| |
| spi0_pins: spi0 { |
| pins = "PC0", "PC1", "PC2", "PC3"; |
| function = "spi0"; |
| }; |
| |
| spi1_pins: spi1 { |
| pins = "PD0", "PD1", "PD2", "PD3"; |
| function = "spi1"; |
| }; |
| |
| uart0_pins_a: uart0 { |
| pins = "PB8", "PB9"; |
| function = "uart0"; |
| }; |
| |
| uart1_pins: uart1_pins { |
| pins = "PG6", "PG7"; |
| function = "uart1"; |
| }; |
| |
| uart1_rts_cts_pins: uart1_rts_cts_pins { |
| pins = "PG8", "PG9"; |
| function = "uart1"; |
| }; |
| |
| uart2_pins: uart2-pins { |
| pins = "PB0", "PB1"; |
| function = "uart2"; |
| }; |
| |
| uart3_pins: uart3-pins { |
| pins = "PD0", "PD1"; |
| function = "uart3"; |
| }; |
| |
| uart4_pins: uart4-pins { |
| pins = "PD2", "PD3"; |
| function = "uart4"; |
| }; |
| |
| uart4_rts_cts_pins: uart4-rts-cts-pins { |
| pins = "PD4", "PD5"; |
| function = "uart4"; |
| }; |
| }; |
| |
| spdif: spdif@1c21000 { |
| #sound-dai-cells = <0>; |
| compatible = "allwinner,sun50i-a64-spdif", |
| "allwinner,sun8i-h3-spdif"; |
| reg = <0x01c21000 0x400>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; |
| resets = <&ccu RST_BUS_SPDIF>; |
| clock-names = "apb", "spdif"; |
| dmas = <&dma 2>; |
| dma-names = "tx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spdif_tx_pin>; |
| status = "disabled"; |
| }; |
| |
| i2s0: i2s@1c22000 { |
| #sound-dai-cells = <0>; |
| compatible = "allwinner,sun50i-a64-i2s", |
| "allwinner,sun8i-h3-i2s"; |
| reg = <0x01c22000 0x400>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; |
| clock-names = "apb", "mod"; |
| resets = <&ccu RST_BUS_I2S0>; |
| dma-names = "rx", "tx"; |
| dmas = <&dma 3>, <&dma 3>; |
| status = "disabled"; |
| }; |
| |
| i2s1: i2s@1c22400 { |
| #sound-dai-cells = <0>; |
| compatible = "allwinner,sun50i-a64-i2s", |
| "allwinner,sun8i-h3-i2s"; |
| reg = <0x01c22400 0x400>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; |
| clock-names = "apb", "mod"; |
| resets = <&ccu RST_BUS_I2S1>; |
| dma-names = "rx", "tx"; |
| dmas = <&dma 4>, <&dma 4>; |
| status = "disabled"; |
| }; |
| |
| uart0: serial@1c28000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28000 0x400>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&ccu CLK_BUS_UART0>; |
| resets = <&ccu RST_BUS_UART0>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@1c28400 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28400 0x400>; |
| interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&ccu CLK_BUS_UART1>; |
| resets = <&ccu RST_BUS_UART1>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@1c28800 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28800 0x400>; |
| interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&ccu CLK_BUS_UART2>; |
| resets = <&ccu RST_BUS_UART2>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@1c28c00 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c28c00 0x400>; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&ccu CLK_BUS_UART3>; |
| resets = <&ccu RST_BUS_UART3>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@1c29000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x01c29000 0x400>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&ccu CLK_BUS_UART4>; |
| resets = <&ccu RST_BUS_UART4>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@1c2ac00 { |
| compatible = "allwinner,sun6i-a31-i2c"; |
| reg = <0x01c2ac00 0x400>; |
| interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_I2C0>; |
| resets = <&ccu RST_BUS_I2C0>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| i2c1: i2c@1c2b000 { |
| compatible = "allwinner,sun6i-a31-i2c"; |
| reg = <0x01c2b000 0x400>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_I2C1>; |
| resets = <&ccu RST_BUS_I2C1>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| i2c2: i2c@1c2b400 { |
| compatible = "allwinner,sun6i-a31-i2c"; |
| reg = <0x01c2b400 0x400>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_I2C2>; |
| resets = <&ccu RST_BUS_I2C2>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| |
| spi0: spi@1c68000 { |
| compatible = "allwinner,sun8i-h3-spi"; |
| reg = <0x01c68000 0x1000>; |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; |
| clock-names = "ahb", "mod"; |
| dmas = <&dma 23>, <&dma 23>; |
| dma-names = "rx", "tx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi0_pins>; |
| resets = <&ccu RST_BUS_SPI0>; |
| status = "disabled"; |
| num-cs = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| spi1: spi@1c69000 { |
| compatible = "allwinner,sun8i-h3-spi"; |
| reg = <0x01c69000 0x1000>; |
| interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; |
| clock-names = "ahb", "mod"; |
| dmas = <&dma 24>, <&dma 24>; |
| dma-names = "rx", "tx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi1_pins>; |
| resets = <&ccu RST_BUS_SPI1>; |
| status = "disabled"; |
| num-cs = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| emac: ethernet@1c30000 { |
| compatible = "allwinner,sun50i-a64-emac"; |
| syscon = <&syscon>; |
| reg = <0x01c30000 0x10000>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "macirq"; |
| resets = <&ccu RST_BUS_EMAC>; |
| reset-names = "stmmaceth"; |
| clocks = <&ccu CLK_BUS_EMAC>; |
| clock-names = "stmmaceth"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| mdio: mdio { |
| compatible = "snps,dwmac-mdio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| gic: interrupt-controller@1c81000 { |
| compatible = "arm,gic-400"; |
| reg = <0x01c81000 0x1000>, |
| <0x01c82000 0x2000>, |
| <0x01c84000 0x2000>, |
| <0x01c86000 0x2000>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| }; |
| |
| rtc: rtc@1f00000 { |
| compatible = "allwinner,sun6i-a31-rtc"; |
| reg = <0x01f00000 0x54>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| r_intc: interrupt-controller@1f00c00 { |
| compatible = "allwinner,sun50i-a64-r-intc", |
| "allwinner,sun6i-a31-r-intc"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| reg = <0x01f00c00 0x400>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| r_ccu: clock@1f01400 { |
| compatible = "allwinner,sun50i-a64-r-ccu"; |
| reg = <0x01f01400 0x100>; |
| clocks = <&osc24M>, <&osc32k>, <&iosc>, |
| <&ccu 11>; |
| clock-names = "hosc", "losc", "iosc", "pll-periph"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| r_pio: pinctrl@1f02c00 { |
| compatible = "allwinner,sun50i-a64-r-pinctrl"; |
| reg = <0x01f02c00 0x400>; |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; |
| clock-names = "apb", "hosc", "losc"; |
| gpio-controller; |
| #gpio-cells = <3>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| |
| r_rsb_pins: rsb { |
| pins = "PL0", "PL1"; |
| function = "s_rsb"; |
| }; |
| }; |
| |
| r_rsb: rsb@1f03400 { |
| compatible = "allwinner,sun8i-a23-rsb"; |
| reg = <0x01f03400 0x400>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&r_ccu 6>; |
| clock-frequency = <3000000>; |
| resets = <&r_ccu 2>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&r_rsb_pins>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| wdt0: watchdog@1c20ca0 { |
| compatible = "allwinner,sun50i-a64-wdt", |
| "allwinner,sun6i-a31-wdt"; |
| reg = <0x01c20ca0 0x20>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| }; |
