drivers/clk/qcom/dispcc-sc7180.c - third_party/linux - Git at Google

 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2019, 2022, The Linux Foundation. All rights reserved.
  */

 #include <linux/clk-provider.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>

 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>

 #include "clk-alpha-pll.h"
 #include "clk-branch.h"
 #include "clk-rcg.h"
 #include "clk-regmap-divider.h"
 #include "common.h"
 #include "gdsc.h"

 enum {
 	P_BI_TCXO,
 	P_CHIP_SLEEP_CLK,
 	P_CORE_BI_PLL_TEST_SE,
 	P_DISP_CC_PLL0_OUT_EVEN,
 	P_DISP_CC_PLL0_OUT_MAIN,
 	P_DP_PHY_PLL_LINK_CLK,
 	P_DP_PHY_PLL_VCO_DIV_CLK,
 	P_DSI0_PHY_PLL_OUT_BYTECLK,
 	P_DSI0_PHY_PLL_OUT_DSICLK,
 	P_GPLL0_OUT_MAIN,
 };

 static const struct pll_vco fabia_vco[] = {
 	{ 249600000, 2000000000, 0 },
 };

 static struct clk_alpha_pll disp_cc_pll0 = {
 	.offset = 0x0,
 	.vco_table = fabia_vco,
 	.num_vco = ARRAY_SIZE(fabia_vco),
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_pll0",
 			.parent_data = &(const struct clk_parent_data){
 				.fw_name = "bi_tcxo",
 			},
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_fabia_ops,
 		},
 	},
 };

 static const struct clk_div_table post_div_table_disp_cc_pll0_out_even[] = {
 	{ 0x0, 1 },
 	{ }
 };

 static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = {
 	.offset = 0x0,
 	.post_div_shift = 8,
 	.post_div_table = post_div_table_disp_cc_pll0_out_even,
 	.num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_even),
 	.width = 4,
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_pll0_out_even",
 		.parent_data = &(const struct clk_parent_data){
 			.hw = &disp_cc_pll0.clkr.hw,
 		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
 	},
 };

 static const struct parent_map disp_cc_parent_map_0[] = {
 	{ P_BI_TCXO, 0 },
 };

 static const struct clk_parent_data disp_cc_parent_data_0[] = {
 	{ .fw_name = "bi_tcxo" },
 };

 static const struct parent_map disp_cc_parent_map_1[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_DP_PHY_PLL_LINK_CLK, 1 },
 	{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
 };

 static const struct clk_parent_data disp_cc_parent_data_1[] = {
 	{ .fw_name = "bi_tcxo" },
 	{ .fw_name = "dp_phy_pll_link_clk" },
 	{ .fw_name = "dp_phy_pll_vco_div_clk" },
 };

 static const struct parent_map disp_cc_parent_map_2[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
 };

 static const struct clk_parent_data disp_cc_parent_data_2[] = {
 	{ .fw_name = "bi_tcxo" },
 	{ .fw_name = "dsi0_phy_pll_out_byteclk" },
 };

 static const struct parent_map disp_cc_parent_map_3[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
 	{ P_GPLL0_OUT_MAIN, 4 },
 	{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
 };

 static const struct clk_parent_data disp_cc_parent_data_3[] = {
 	{ .fw_name = "bi_tcxo" },
 	{ .hw = &disp_cc_pll0.clkr.hw },
 	{ .fw_name = "gcc_disp_gpll0_clk_src" },
 	{ .hw = &disp_cc_pll0_out_even.clkr.hw },
 };

 static const struct parent_map disp_cc_parent_map_4[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_GPLL0_OUT_MAIN, 4 },
 };

 static const struct clk_parent_data disp_cc_parent_data_4[] = {
 	{ .fw_name = "bi_tcxo" },
 	{ .fw_name = "gcc_disp_gpll0_clk_src" },
 };

 static const struct parent_map disp_cc_parent_map_5[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 };

 static const struct clk_parent_data disp_cc_parent_data_5[] = {
 	{ .fw_name = "bi_tcxo" },
 	{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
 };

 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
 	F(19200000, P_BI_TCXO, 1, 0, 0),
 	F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 	F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 	{ }
 };

 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
 	.cmd_rcgr = 0x22bc,
 	.mnd_width = 0,
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_4,
 	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_mdss_ahb_clk_src",
 		.parent_data = disp_cc_parent_data_4,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_shared_ops,
 	},
 };

 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
 	.cmd_rcgr = 0x2110,
 	.mnd_width = 0,
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_2,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_mdss_byte0_clk_src",
 		.parent_data = disp_cc_parent_data_2,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_byte2_ops,
 	},
 };

 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
 	F(19200000, P_BI_TCXO, 1, 0, 0),
 	{ }
 };

 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
 	.cmd_rcgr = 0x21dc,
 	.mnd_width = 0,
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_0,
 	.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_mdss_dp_aux_clk_src",
 		.parent_data = disp_cc_parent_data_0,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 		.ops = &clk_rcg2_ops,
 	},
 };

 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
 	.cmd_rcgr = 0x2194,
 	.mnd_width = 0,
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_1,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_mdss_dp_crypto_clk_src",
 		.parent_data = disp_cc_parent_data_1,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 		.ops = &clk_byte2_ops,
 	},
 };

 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
 	.cmd_rcgr = 0x2178,
 	.mnd_width = 0,
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_1,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_mdss_dp_link_clk_src",
 		.parent_data = disp_cc_parent_data_1,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 		.ops = &clk_byte2_ops,
 	},
 };

 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
 	.cmd_rcgr = 0x21ac,
 	.mnd_width = 16,
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_1,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_mdss_dp_pixel_clk_src",
 		.parent_data = disp_cc_parent_data_1,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 		.ops = &clk_dp_ops,
 	},
 };

 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
 	.cmd_rcgr = 0x2148,
 	.mnd_width = 0,
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_2,
 	.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_mdss_esc0_clk_src",
 		.parent_data = disp_cc_parent_data_2,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 		.ops = &clk_rcg2_ops,
 	},
 };

 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
 	F(19200000, P_BI_TCXO, 1, 0, 0),
 	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 	F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
 	F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 	{ }
 };

 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
 	.cmd_rcgr = 0x20c8,
 	.mnd_width = 0,
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_3,
 	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_mdss_mdp_clk_src",
 		.parent_data = disp_cc_parent_data_3,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };

 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
 	.cmd_rcgr = 0x2098,
 	.mnd_width = 8,
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_5,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_mdss_pclk0_clk_src",
 		.parent_data = disp_cc_parent_data_5,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_pixel_ops,
 	},
 };

 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
 	.cmd_rcgr = 0x20e0,
 	.mnd_width = 0,
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_3,
 	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_mdss_rot_clk_src",
 		.parent_data = disp_cc_parent_data_3,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };

 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
 	.cmd_rcgr = 0x20f8,
 	.mnd_width = 0,
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_0,
 	.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_mdss_vsync_clk_src",
 		.parent_data = disp_cc_parent_data_0,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };

 static struct clk_branch disp_cc_mdss_ahb_clk = {
 	.halt_reg = 0x2080,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x2080,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_ahb_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_byte0_clk = {
 	.halt_reg = 0x2028,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x2028,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_byte0_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
 	.reg = 0x2128,
 	.shift = 0,
 	.width = 2,
 	.clkr.hw.init = &(struct clk_init_data) {
 		.name = "disp_cc_mdss_byte0_div_clk_src",
 		.parent_data = &(const struct clk_parent_data){
 			.hw = &disp_cc_mdss_byte0_clk_src.clkr.hw
 		},
 		.num_parents = 1,
 		.ops = &clk_regmap_div_ops,
 	},
 };

 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
 	.reg = 0x2190,
 	.shift = 0,
 	.width = 2,
 	.clkr.hw.init = &(struct clk_init_data) {
 		.name = "disp_cc_mdss_dp_link_div_clk_src",
 		.parent_data = &(const struct clk_parent_data){
 			.hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw
 		},
 		.num_parents = 1,
 		.ops = &clk_regmap_div_ops,
 	},
 };

 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
 	.halt_reg = 0x202c,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x202c,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_byte0_intf_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
 	.halt_reg = 0x2054,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x2054,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_dp_aux_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
 	.halt_reg = 0x2048,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x2048,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_dp_crypto_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_dp_link_clk = {
 	.halt_reg = 0x2040,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x2040,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_dp_link_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
 	.halt_reg = 0x2044,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x2044,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_dp_link_intf_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
 	.halt_reg = 0x204c,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x204c,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_dp_pixel_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_esc0_clk = {
 	.halt_reg = 0x2038,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x2038,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_esc0_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_esc0_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_mdp_clk = {
 	.halt_reg = 0x200c,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x200c,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_mdp_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
 	.halt_reg = 0x201c,
 	.halt_check = BRANCH_VOTED,
 	.clkr = {
 		.enable_reg = 0x201c,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_mdp_lut_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
 	.halt_reg = 0x4004,
 	.halt_check = BRANCH_VOTED,
 	.clkr = {
 		.enable_reg = 0x4004,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_non_gdsc_ahb_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_pclk0_clk = {
 	.halt_reg = 0x2004,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x2004,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_pclk0_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_rot_clk = {
 	.halt_reg = 0x2014,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x2014,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_rot_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_rot_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
 	.halt_reg = 0x4008,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x4008,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_rscc_vsync_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch disp_cc_mdss_vsync_clk = {
 	.halt_reg = 0x2024,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x2024,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "disp_cc_mdss_vsync_clk",
 			.parent_data = &(const struct clk_parent_data){
 				.hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct gdsc mdss_gdsc = {
 	.gdscr = 0x3000,
 	.en_rest_wait_val = 0x2,
 	.en_few_wait_val = 0x2,
 	.clk_dis_wait_val = 0xf,
 	.pd = {
 		.name = "mdss_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
 	.flags = HW_CTRL,
 };

 static struct gdsc *disp_cc_sc7180_gdscs[] = {
 	[MDSS_GDSC] = &mdss_gdsc,
 };

 static struct clk_regmap *disp_cc_sc7180_clocks[] = {
 	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
 	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
 	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
 	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
 	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
 	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
 	[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
 	[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
 	[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
 	[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
 	[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
 	[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
 	[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
 				&disp_cc_mdss_dp_link_div_clk_src.clkr,
 	[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
 	[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
 	[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
 	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
 	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
 	[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
 	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
 	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
 	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
 	[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
 	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
 	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
 	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
 	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
 	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
 	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
 	[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
 	[DISP_CC_PLL0_OUT_EVEN] = &disp_cc_pll0_out_even.clkr,
 };

 static const struct regmap_config disp_cc_sc7180_regmap_config = {
 	.reg_bits = 32,
 	.reg_stride = 4,
 	.val_bits = 32,
 	.max_register = 0x10000,
 	.fast_io = true,
 };

 static const struct qcom_cc_desc disp_cc_sc7180_desc = {
 	.config = &disp_cc_sc7180_regmap_config,
 	.clks = disp_cc_sc7180_clocks,
 	.num_clks = ARRAY_SIZE(disp_cc_sc7180_clocks),
 	.gdscs = disp_cc_sc7180_gdscs,
 	.num_gdscs = ARRAY_SIZE(disp_cc_sc7180_gdscs),
 };

 static const struct of_device_id disp_cc_sc7180_match_table[] = {
 	{ .compatible = "qcom,sc7180-dispcc" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, disp_cc_sc7180_match_table);

 static int disp_cc_sc7180_probe(struct platform_device *pdev)
 {
 	struct regmap *regmap;
 	struct alpha_pll_config disp_cc_pll_config = {};

 	regmap = qcom_cc_map(pdev, &disp_cc_sc7180_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);

 	/* 1380MHz configuration */
 	disp_cc_pll_config.l = 0x47;
 	disp_cc_pll_config.alpha = 0xe000;
 	disp_cc_pll_config.user_ctl_val = 0x00000001;
 	disp_cc_pll_config.user_ctl_hi_val = 0x00004805;

 	clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config);

 	return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap);
 }

 static struct platform_driver disp_cc_sc7180_driver = {
 	.probe = disp_cc_sc7180_probe,
 	.driver = {
 		.name = "sc7180-dispcc",
 		.of_match_table = disp_cc_sc7180_match_table,
 	},
 };

 static int __init disp_cc_sc7180_init(void)
 {
 	return platform_driver_register(&disp_cc_sc7180_driver);
 }
 subsys_initcall(disp_cc_sc7180_init);

 static void __exit disp_cc_sc7180_exit(void)
 {
 	platform_driver_unregister(&disp_cc_sc7180_driver);
 }
 module_exit(disp_cc_sc7180_exit);

 MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver");
 MODULE_LICENSE("GPL v2");
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (c) 2019, 2022, The Linux Foundation. All rights reserved.
	*/

	#include <linux/clk-provider.h>
	#include <linux/module.h>
	#include <linux/platform_device.h>
	#include <linux/regmap.h>

	#include <dt-bindings/clock/qcom,dispcc-sc7180.h>

	#include "clk-alpha-pll.h"
	#include "clk-branch.h"
	#include "clk-rcg.h"
	#include "clk-regmap-divider.h"
	#include "common.h"
	#include "gdsc.h"

	enum {
	P_BI_TCXO,
	P_CHIP_SLEEP_CLK,
	P_CORE_BI_PLL_TEST_SE,
	P_DISP_CC_PLL0_OUT_EVEN,
	P_DISP_CC_PLL0_OUT_MAIN,
	P_DP_PHY_PLL_LINK_CLK,
	P_DP_PHY_PLL_VCO_DIV_CLK,
	P_DSI0_PHY_PLL_OUT_BYTECLK,
	P_DSI0_PHY_PLL_OUT_DSICLK,
	P_GPLL0_OUT_MAIN,
	};

	static const struct pll_vco fabia_vco[] = {
	{ 249600000, 2000000000, 0 },
	};

	static struct clk_alpha_pll disp_cc_pll0 = {
	.offset = 0x0,
	.vco_table = fabia_vco,
	.num_vco = ARRAY_SIZE(fabia_vco),
	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
	.clkr = {
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_pll0",
	.parent_data = &(const struct clk_parent_data){
	.fw_name = "bi_tcxo",
	},
	.num_parents = 1,
	.ops = &clk_alpha_pll_fabia_ops,
	},
	},
	};

	static const struct clk_div_table post_div_table_disp_cc_pll0_out_even[] = {
	{ 0x0, 1 },
	{ }
	};

	static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = {
	.offset = 0x0,
	.post_div_shift = 8,
	.post_div_table = post_div_table_disp_cc_pll0_out_even,
	.num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_even),
	.width = 4,
	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
	.clkr.hw.init = &(struct clk_init_data){
	.name = "disp_cc_pll0_out_even",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_pll0.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_alpha_pll_postdiv_fabia_ops,
	},
	};

	static const struct parent_map disp_cc_parent_map_0[] = {
	{ P_BI_TCXO, 0 },
	};

	static const struct clk_parent_data disp_cc_parent_data_0[] = {
	{ .fw_name = "bi_tcxo" },
	};

	static const struct parent_map disp_cc_parent_map_1[] = {
	{ P_BI_TCXO, 0 },
	{ P_DP_PHY_PLL_LINK_CLK, 1 },
	{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
	};

	static const struct clk_parent_data disp_cc_parent_data_1[] = {
	{ .fw_name = "bi_tcxo" },
	{ .fw_name = "dp_phy_pll_link_clk" },
	{ .fw_name = "dp_phy_pll_vco_div_clk" },
	};

	static const struct parent_map disp_cc_parent_map_2[] = {
	{ P_BI_TCXO, 0 },
	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
	};

	static const struct clk_parent_data disp_cc_parent_data_2[] = {
	{ .fw_name = "bi_tcxo" },
	{ .fw_name = "dsi0_phy_pll_out_byteclk" },
	};

	static const struct parent_map disp_cc_parent_map_3[] = {
	{ P_BI_TCXO, 0 },
	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
	{ P_GPLL0_OUT_MAIN, 4 },
	{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
	};

	static const struct clk_parent_data disp_cc_parent_data_3[] = {
	{ .fw_name = "bi_tcxo" },
	{ .hw = &disp_cc_pll0.clkr.hw },
	{ .fw_name = "gcc_disp_gpll0_clk_src" },
	{ .hw = &disp_cc_pll0_out_even.clkr.hw },
	};

	static const struct parent_map disp_cc_parent_map_4[] = {
	{ P_BI_TCXO, 0 },
	{ P_GPLL0_OUT_MAIN, 4 },
	};

	static const struct clk_parent_data disp_cc_parent_data_4[] = {
	{ .fw_name = "bi_tcxo" },
	{ .fw_name = "gcc_disp_gpll0_clk_src" },
	};

	static const struct parent_map disp_cc_parent_map_5[] = {
	{ P_BI_TCXO, 0 },
	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
	};

	static const struct clk_parent_data disp_cc_parent_data_5[] = {
	{ .fw_name = "bi_tcxo" },
	{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
	};

	static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
	F(19200000, P_BI_TCXO, 1, 0, 0),
	F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
	F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
	{ }
	};

	static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
	.cmd_rcgr = 0x22bc,
	.mnd_width = 0,
	.hid_width = 5,
	.parent_map = disp_cc_parent_map_4,
	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_ahb_clk_src",
	.parent_data = disp_cc_parent_data_4,
	.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_rcg2_shared_ops,
	},
	};

	static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
	.cmd_rcgr = 0x2110,
	.mnd_width = 0,
	.hid_width = 5,
	.parent_map = disp_cc_parent_map_2,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_byte0_clk_src",
	.parent_data = disp_cc_parent_data_2,
	.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_byte2_ops,
	},
	};

	static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
	F(19200000, P_BI_TCXO, 1, 0, 0),
	{ }
	};

	static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
	.cmd_rcgr = 0x21dc,
	.mnd_width = 0,
	.hid_width = 5,
	.parent_map = disp_cc_parent_map_0,
	.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_dp_aux_clk_src",
	.parent_data = disp_cc_parent_data_0,
	.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
	.ops = &clk_rcg2_ops,
	},
	};

	static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
	.cmd_rcgr = 0x2194,
	.mnd_width = 0,
	.hid_width = 5,
	.parent_map = disp_cc_parent_map_1,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_dp_crypto_clk_src",
	.parent_data = disp_cc_parent_data_1,
	.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
	.ops = &clk_byte2_ops,
	},
	};

	static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
	.cmd_rcgr = 0x2178,
	.mnd_width = 0,
	.hid_width = 5,
	.parent_map = disp_cc_parent_map_1,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_dp_link_clk_src",
	.parent_data = disp_cc_parent_data_1,
	.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
	.ops = &clk_byte2_ops,
	},
	};

	static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
	.cmd_rcgr = 0x21ac,
	.mnd_width = 16,
	.hid_width = 5,
	.parent_map = disp_cc_parent_map_1,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_dp_pixel_clk_src",
	.parent_data = disp_cc_parent_data_1,
	.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
	.ops = &clk_dp_ops,
	},
	};

	static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
	.cmd_rcgr = 0x2148,
	.mnd_width = 0,
	.hid_width = 5,
	.parent_map = disp_cc_parent_map_2,
	.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_esc0_clk_src",
	.parent_data = disp_cc_parent_data_2,
	.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
	.ops = &clk_rcg2_ops,
	},
	};

	static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
	F(19200000, P_BI_TCXO, 1, 0, 0),
	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
	F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
	F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
	{ }
	};

	static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
	.cmd_rcgr = 0x20c8,
	.mnd_width = 0,
	.hid_width = 5,
	.parent_map = disp_cc_parent_map_3,
	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_mdp_clk_src",
	.parent_data = disp_cc_parent_data_3,
	.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
	.ops = &clk_rcg2_shared_ops,
	},
	};

	static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
	.cmd_rcgr = 0x2098,
	.mnd_width = 8,
	.hid_width = 5,
	.parent_map = disp_cc_parent_map_5,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_pclk0_clk_src",
	.parent_data = disp_cc_parent_data_5,
	.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_pixel_ops,
	},
	};

	static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
	.cmd_rcgr = 0x20e0,
	.mnd_width = 0,
	.hid_width = 5,
	.parent_map = disp_cc_parent_map_3,
	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_rot_clk_src",
	.parent_data = disp_cc_parent_data_3,
	.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
	.ops = &clk_rcg2_shared_ops,
	},
	};

	static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
	.cmd_rcgr = 0x20f8,
	.mnd_width = 0,
	.hid_width = 5,
	.parent_map = disp_cc_parent_map_0,
	.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_vsync_clk_src",
	.parent_data = disp_cc_parent_data_0,
	.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
	.ops = &clk_rcg2_shared_ops,
	},
	};

	static struct clk_branch disp_cc_mdss_ahb_clk = {
	.halt_reg = 0x2080,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x2080,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_ahb_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_byte0_clk = {
	.halt_reg = 0x2028,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x2028,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_byte0_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
	.reg = 0x2128,
	.shift = 0,
	.width = 2,
	.clkr.hw.init = &(struct clk_init_data) {
	.name = "disp_cc_mdss_byte0_div_clk_src",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_byte0_clk_src.clkr.hw
	},
	.num_parents = 1,
	.ops = &clk_regmap_div_ops,
	},
	};

	static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
	.reg = 0x2190,
	.shift = 0,
	.width = 2,
	.clkr.hw.init = &(struct clk_init_data) {
	.name = "disp_cc_mdss_dp_link_div_clk_src",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw
	},
	.num_parents = 1,
	.ops = &clk_regmap_div_ops,
	},
	};

	static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
	.halt_reg = 0x202c,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x202c,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_byte0_intf_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_dp_aux_clk = {
	.halt_reg = 0x2054,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x2054,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_dp_aux_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
	.halt_reg = 0x2048,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x2048,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_dp_crypto_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_dp_link_clk = {
	.halt_reg = 0x2040,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x2040,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_dp_link_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
	.halt_reg = 0x2044,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x2044,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_dp_link_intf_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
	.halt_reg = 0x204c,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x204c,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_dp_pixel_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_esc0_clk = {
	.halt_reg = 0x2038,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x2038,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_esc0_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_esc0_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_mdp_clk = {
	.halt_reg = 0x200c,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x200c,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_mdp_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
	.halt_reg = 0x201c,
	.halt_check = BRANCH_VOTED,
	.clkr = {
	.enable_reg = 0x201c,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_mdp_lut_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
	.halt_reg = 0x4004,
	.halt_check = BRANCH_VOTED,
	.clkr = {
	.enable_reg = 0x4004,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_non_gdsc_ahb_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_pclk0_clk = {
	.halt_reg = 0x2004,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x2004,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_pclk0_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_rot_clk = {
	.halt_reg = 0x2014,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x2014,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_rot_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_rot_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
	.halt_reg = 0x4008,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x4008,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_rscc_vsync_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch disp_cc_mdss_vsync_clk = {
	.halt_reg = 0x2024,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x2024,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "disp_cc_mdss_vsync_clk",
	.parent_data = &(const struct clk_parent_data){
	.hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct gdsc mdss_gdsc = {
	.gdscr = 0x3000,
	.en_rest_wait_val = 0x2,
	.en_few_wait_val = 0x2,
	.clk_dis_wait_val = 0xf,
	.pd = {
	.name = "mdss_gdsc",
	},
	.pwrsts = PWRSTS_OFF_ON,
	.flags = HW_CTRL,
	};

	static struct gdsc *disp_cc_sc7180_gdscs[] = {
	[MDSS_GDSC] = &mdss_gdsc,
	};

	static struct clk_regmap *disp_cc_sc7180_clocks[] = {
	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
	[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
	[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
	[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
	[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
	[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
	[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
	[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
	&disp_cc_mdss_dp_link_div_clk_src.clkr,
	[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
	[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
	[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
	[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
	[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
	[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
	[DISP_CC_PLL0_OUT_EVEN] = &disp_cc_pll0_out_even.clkr,
	};

	static const struct regmap_config disp_cc_sc7180_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = 0x10000,
	.fast_io = true,
	};

	static const struct qcom_cc_desc disp_cc_sc7180_desc = {
	.config = &disp_cc_sc7180_regmap_config,
	.clks = disp_cc_sc7180_clocks,
	.num_clks = ARRAY_SIZE(disp_cc_sc7180_clocks),
	.gdscs = disp_cc_sc7180_gdscs,
	.num_gdscs = ARRAY_SIZE(disp_cc_sc7180_gdscs),
	};

	static const struct of_device_id disp_cc_sc7180_match_table[] = {
	{ .compatible = "qcom,sc7180-dispcc" },
	{ }
	};
	MODULE_DEVICE_TABLE(of, disp_cc_sc7180_match_table);

	static int disp_cc_sc7180_probe(struct platform_device *pdev)
	{
	struct regmap *regmap;
	struct alpha_pll_config disp_cc_pll_config = {};

	regmap = qcom_cc_map(pdev, &disp_cc_sc7180_desc);
	if (IS_ERR(regmap))
	return PTR_ERR(regmap);

	/* 1380MHz configuration */
	disp_cc_pll_config.l = 0x47;
	disp_cc_pll_config.alpha = 0xe000;
	disp_cc_pll_config.user_ctl_val = 0x00000001;
	disp_cc_pll_config.user_ctl_hi_val = 0x00004805;

	clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config);

	return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap);
	}

	static struct platform_driver disp_cc_sc7180_driver = {
	.probe = disp_cc_sc7180_probe,
	.driver = {
	.name = "sc7180-dispcc",
	.of_match_table = disp_cc_sc7180_match_table,
	},
	};

	static int __init disp_cc_sc7180_init(void)
	{
	return platform_driver_register(&disp_cc_sc7180_driver);
	}
	subsys_initcall(disp_cc_sc7180_init);

	static void __exit disp_cc_sc7180_exit(void)
	{
	platform_driver_unregister(&disp_cc_sc7180_driver);
	}
	module_exit(disp_cc_sc7180_exit);

	MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver");
	MODULE_LICENSE("GPL v2");