| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright (C) 2020 MediaTek Inc. |
| * Author: Seiya Wang <seiya.wang@mediatek.com> |
| */ |
| |
| /dts-v1/; |
| #include <dt-bindings/clock/mt8192-clk.h> |
| #include <dt-bindings/gce/mt8192-gce.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/memory/mt8192-larb-port.h> |
| #include <dt-bindings/pinctrl/mt8192-pinfunc.h> |
| #include <dt-bindings/phy/phy.h> |
| #include <dt-bindings/power/mt8192-power.h> |
| #include <dt-bindings/reset/ti-syscon.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| compatible = "mediatek,mt8192"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c4 = &i2c4; |
| i2c5 = &i2c5; |
| i2c6 = &i2c6; |
| i2c7 = &i2c7; |
| i2c8 = &i2c8; |
| i2c9 = &i2c9; |
| ovl0 = &ovl0; |
| ovl-2l0 = &ovl_2l0; |
| ovl-2l2 = &ovl_2l2; |
| rdma0 = &rdma0; |
| rdma4 = &rdma4; |
| }; |
| |
| clk13m: fixed-factor-clock-13m { |
| compatible = "fixed-factor-clock"; |
| #clock-cells = <0>; |
| clocks = <&clk26m>; |
| clock-div = <2>; |
| clock-mult = <1>; |
| clock-output-names = "clk13m"; |
| }; |
| |
| clk26m: oscillator0 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <26000000>; |
| clock-output-names = "clk26m"; |
| }; |
| |
| clk32k: oscillator1 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| clock-output-names = "clk32k"; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x000>; |
| enable-method = "psci"; |
| performance-domains = <&performance 0>; |
| clock-frequency = <1701000000>; |
| cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; |
| next-level-cache = <&l2_0>; |
| capacity-dmips-mhz = <530>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x100>; |
| enable-method = "psci"; |
| performance-domains = <&performance 0>; |
| clock-frequency = <1701000000>; |
| cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; |
| next-level-cache = <&l2_0>; |
| capacity-dmips-mhz = <530>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x200>; |
| enable-method = "psci"; |
| performance-domains = <&performance 0>; |
| clock-frequency = <1701000000>; |
| cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; |
| next-level-cache = <&l2_0>; |
| capacity-dmips-mhz = <530>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x300>; |
| enable-method = "psci"; |
| performance-domains = <&performance 0>; |
| clock-frequency = <1701000000>; |
| cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; |
| next-level-cache = <&l2_0>; |
| capacity-dmips-mhz = <530>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a76"; |
| reg = <0x400>; |
| enable-method = "psci"; |
| performance-domains = <&performance 1>; |
| clock-frequency = <2171000000>; |
| cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; |
| next-level-cache = <&l2_1>; |
| capacity-dmips-mhz = <1024>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a76"; |
| reg = <0x500>; |
| enable-method = "psci"; |
| performance-domains = <&performance 1>; |
| clock-frequency = <2171000000>; |
| cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; |
| next-level-cache = <&l2_1>; |
| capacity-dmips-mhz = <1024>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a76"; |
| reg = <0x600>; |
| enable-method = "psci"; |
| performance-domains = <&performance 1>; |
| clock-frequency = <2171000000>; |
| cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; |
| next-level-cache = <&l2_1>; |
| capacity-dmips-mhz = <1024>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a76"; |
| reg = <0x700>; |
| enable-method = "psci"; |
| performance-domains = <&performance 1>; |
| clock-frequency = <2171000000>; |
| cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; |
| next-level-cache = <&l2_1>; |
| capacity-dmips-mhz = <1024>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| core4 { |
| cpu = <&cpu4>; |
| }; |
| core5 { |
| cpu = <&cpu5>; |
| }; |
| core6 { |
| cpu = <&cpu6>; |
| }; |
| core7 { |
| cpu = <&cpu7>; |
| }; |
| }; |
| }; |
| |
| l2_0: l2-cache0 { |
| compatible = "cache"; |
| next-level-cache = <&l3_0>; |
| }; |
| |
| l2_1: l2-cache1 { |
| compatible = "cache"; |
| next-level-cache = <&l3_0>; |
| }; |
| |
| l3_0: l3-cache { |
| compatible = "cache"; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| cpu_sleep_l: cpu-sleep-l { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x00010001>; |
| local-timer-stop; |
| entry-latency-us = <55>; |
| exit-latency-us = <140>; |
| min-residency-us = <780>; |
| }; |
| cpu_sleep_b: cpu-sleep-b { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x00010001>; |
| local-timer-stop; |
| entry-latency-us = <35>; |
| exit-latency-us = <145>; |
| min-residency-us = <720>; |
| }; |
| cluster_sleep_l: cluster-sleep-l { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x01010002>; |
| local-timer-stop; |
| entry-latency-us = <60>; |
| exit-latency-us = <155>; |
| min-residency-us = <860>; |
| }; |
| cluster_sleep_b: cluster-sleep-b { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x01010002>; |
| local-timer-stop; |
| entry-latency-us = <40>; |
| exit-latency-us = <155>; |
| min-residency-us = <780>; |
| }; |
| }; |
| }; |
| |
| pmu-a55 { |
| compatible = "arm,cortex-a55-pmu"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; |
| }; |
| |
| pmu-a76 { |
| compatible = "arm,cortex-a76-pmu"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| timer: timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; |
| clock-frequency = <13000000>; |
| }; |
| |
| thermal-zones { |
| soc_max { |
| polling-delay = <1000>; /* milliseconds */ |
| polling-delay-passive = <1000>; /* milliseconds */ |
| sustainable-power = <1500>; |
| thermal-sensors = <&lvts 0>; |
| |
| trips { |
| threshold: trip-point@0 { |
| temperature = <68000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| target: target@1 { |
| temperature = <85000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| soc_max_crit: soc_max_crit { |
| temperature = <115000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&target>; |
| cooling-device = <&cpu0 |
| THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>, |
| <&cpu1 |
| THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>, |
| <&cpu2 |
| THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>, |
| <&cpu3 |
| THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>; |
| contribution = <3072>; |
| }; |
| map1 { |
| trip = <&target>; |
| cooling-device = <&cpu4 |
| THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>, |
| <&cpu5 |
| THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>, |
| <&cpu6 |
| THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>, |
| <&cpu7 |
| THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>; |
| contribution = <1024>; |
| }; |
| }; |
| }; |
| cpu_big1 { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 1>; |
| }; |
| cpu_big2 { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 2>; |
| }; |
| cpu_big3 { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 3>; |
| }; |
| cpu_big4 { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 4>; |
| }; |
| cci1 { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 5>; |
| }; |
| cci2 { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 6>; |
| }; |
| cpu_little1 { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 7>; |
| }; |
| cpu_little2 { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 8>; |
| }; |
| apu { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 9>; |
| }; |
| mlda { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 10>; |
| }; |
| gpu1 { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 11>; |
| }; |
| gpu2 { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 12>; |
| }; |
| infra { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 13>; |
| }; |
| camsys { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 14>; |
| }; |
| md1 { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 15>; |
| }; |
| md2{ |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 16>; |
| }; |
| md3 { |
| polling-delay = <0>; /* milliseconds */ |
| polling-delay-passive = <0>; /* milliseconds */ |
| thermal-sensors = <&lvts 17>; |
| }; |
| }; |
| |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| compatible = "simple-bus"; |
| ranges; |
| |
| performance: performance-controller@0011bc00 { |
| compatible = "mediatek,cpufreq-hw"; |
| reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; |
| #performance-domain-cells = <1>; |
| }; |
| |
| gic: interrupt-controller@c000000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <4>; |
| #redistributor-regions = <1>; |
| interrupt-parent = <&gic>; |
| interrupt-controller; |
| reg = <0 0x0c000000 0 0x40000>, |
| <0 0x0c040000 0 0x200000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; |
| |
| ppi-partitions { |
| ppi_cluster0: interrupt-partition-0 { |
| affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; |
| }; |
| ppi_cluster1: interrupt-partition-1 { |
| affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; |
| }; |
| }; |
| }; |
| |
| topckgen: syscon@10000000 { |
| compatible = "mediatek,mt8192-topckgen", "syscon"; |
| reg = <0 0x10000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| infracfg: infracfg@10001000 { |
| compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; |
| reg = <0 0x10001000 0 0x1000>; |
| #clock-cells = <1>; |
| |
| infracfg_rst: reset-controller { |
| compatible = "mediatek,infra-reset", "ti,syscon-reset"; |
| #reset-cells = <1>; |
| ti,reset-bits = < |
| 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */ |
| 0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */ |
| 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */ |
| 0x730 1 0x734 1 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */ |
| 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */ |
| >; |
| }; |
| }; |
| |
| pericfg: syscon@10003000 { |
| compatible = "mediatek,mt8192-pericfg", "syscon"; |
| reg = <0 0x10003000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| pio: pinctrl@10005000 { |
| compatible = "mediatek,mt8192-pinctrl"; |
| reg = <0 0x10005000 0 0x1000>, |
| <0 0x11c20000 0 0x1000>, |
| <0 0x11d10000 0 0x1000>, |
| <0 0x11d30000 0 0x1000>, |
| <0 0x11d40000 0 0x1000>, |
| <0 0x11e20000 0 0x1000>, |
| <0 0x11e70000 0 0x1000>, |
| <0 0x11ea0000 0 0x1000>, |
| <0 0x11f20000 0 0x1000>, |
| <0 0x11f30000 0 0x1000>, |
| <0 0x1000b000 0 0x1000>; |
| reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", |
| "iocfg_bl", "iocfg_br", "iocfg_lm", |
| "iocfg_lb", "iocfg_rt", "iocfg_lt", |
| "iocfg_tl", "eint"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pio 0 0 220>; |
| interrupt-controller; |
| interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; |
| #interrupt-cells = <2>; |
| }; |
| |
| scpsys: syscon@10006000 { |
| compatible = "syscon", "simple-mfd"; |
| reg = <0 0x10006000 0 0x1000>; |
| #power-domain-cells = <1>; |
| |
| /* System Power Manager */ |
| spm: power-controller { |
| compatible = "mediatek,mt8192-power-controller"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| /* power domain of the SoC */ |
| power-domain@MT8192_POWER_DOMAIN_AUDIO { |
| reg = <MT8192_POWER_DOMAIN_AUDIO>; |
| clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, |
| <&infracfg CLK_INFRA_AUDIO_26M_B>, |
| <&infracfg CLK_INFRA_AUDIO>; |
| clock-names = "audio", "audio1", "audio2"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_CONN { |
| reg = <MT8192_POWER_DOMAIN_CONN>; |
| clocks = <&infracfg CLK_INFRA_PMIC_CONN>; |
| clock-names = "conn"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 { |
| reg = <MT8192_POWER_DOMAIN_MFG0>; |
| clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; |
| clock-names = "mfg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG1 { |
| reg = <MT8192_POWER_DOMAIN_MFG1>; |
| mediatek,infracfg = <&infracfg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG2 { |
| reg = <MT8192_POWER_DOMAIN_MFG2>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG3 { |
| reg = <MT8192_POWER_DOMAIN_MFG3>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG4 { |
| reg = <MT8192_POWER_DOMAIN_MFG4>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG5 { |
| reg = <MT8192_POWER_DOMAIN_MFG5>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_MFG6 { |
| reg = <MT8192_POWER_DOMAIN_MFG6>; |
| #power-domain-cells = <0>; |
| }; |
| }; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_DISP { |
| reg = <MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&topckgen CLK_TOP_DISP_SEL>, |
| <&mmsys CLK_MM_SMI_INFRA>, |
| <&mmsys CLK_MM_SMI_COMMON>, |
| <&mmsys CLK_MM_SMI_GALS>, |
| <&mmsys CLK_MM_SMI_IOMMU>; |
| clock-names = "disp", "disp-0", "disp-1", "disp-2", |
| "disp-3"; |
| mediatek,infracfg = <&infracfg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| power-domain@MT8192_POWER_DOMAIN_IPE { |
| reg = <MT8192_POWER_DOMAIN_IPE>; |
| clocks = <&topckgen CLK_TOP_IPE_SEL>, |
| <&ipesys CLK_IPE_LARB19>, |
| <&ipesys CLK_IPE_LARB20>, |
| <&ipesys CLK_IPE_SMI_SUBCOM>, |
| <&ipesys CLK_IPE_GALS>; |
| clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", |
| "ipe-3"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_ISP { |
| reg = <MT8192_POWER_DOMAIN_ISP>; |
| clocks = <&topckgen CLK_TOP_IMG1_SEL>, |
| <&imgsys CLK_IMG_LARB9>, |
| <&imgsys CLK_IMG_GALS>; |
| clock-names = "isp", "isp-0", "isp-1"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_ISP2 { |
| reg = <MT8192_POWER_DOMAIN_ISP2>; |
| clocks = <&topckgen CLK_TOP_IMG2_SEL>, |
| <&imgsys2 CLK_IMG2_LARB11>, |
| <&imgsys2 CLK_IMG2_GALS>; |
| clock-names = "isp2", "isp2-0", "isp2-1"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_MDP { |
| reg = <MT8192_POWER_DOMAIN_MDP>; |
| clocks = <&topckgen CLK_TOP_MDP_SEL>, |
| <&mdpsys CLK_MDP_SMI0>; |
| clock-names = "mdp", "mdp-0"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_VENC { |
| reg = <MT8192_POWER_DOMAIN_VENC>; |
| clocks = <&topckgen CLK_TOP_VENC_SEL>, |
| <&vencsys CLK_VENC_SET1_VENC>; |
| clock-names = "venc", "venc-0"; |
| mediatek,infracfg = <&infracfg>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_VDEC { |
| reg = <MT8192_POWER_DOMAIN_VDEC>; |
| clocks = <&topckgen CLK_TOP_VDEC_SEL>, |
| <&vdecsys_soc CLK_VDEC_SOC_VDEC>, |
| <&vdecsys_soc CLK_VDEC_SOC_LAT>, |
| <&vdecsys_soc CLK_VDEC_SOC_LARB1>; |
| clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; |
| mediatek,infracfg = <&infracfg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| power-domain@MT8192_POWER_DOMAIN_VDEC2 { |
| reg = <MT8192_POWER_DOMAIN_VDEC2>; |
| clocks = <&vdecsys CLK_VDEC_VDEC>, |
| <&vdecsys CLK_VDEC_LAT>, |
| <&vdecsys CLK_VDEC_LARB1>; |
| clock-names = "vdec2-0", "vdec2-1", |
| "vdec2-2"; |
| #power-domain-cells = <0>; |
| }; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_CAM { |
| reg = <MT8192_POWER_DOMAIN_CAM>; |
| clocks = <&topckgen CLK_TOP_CAM_SEL>, |
| <&camsys CLK_CAM_LARB13>, |
| <&camsys CLK_CAM_LARB14>, |
| <&camsys CLK_CAM_CCU_GALS>, |
| <&camsys CLK_CAM_CAM2MM_GALS>; |
| clock-names = "cam", "cam-0", "cam-1", "cam-2", |
| "cam-3"; |
| mediatek,infracfg = <&infracfg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { |
| reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; |
| clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; |
| clock-names = "cam_rawa-0"; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { |
| reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; |
| clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; |
| clock-names = "cam_rawb-0"; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { |
| reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; |
| clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; |
| clock-names = "cam_rawc-0"; |
| #power-domain-cells = <0>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| watchdog: watchdog@10007000 { |
| compatible = "mediatek,mt8192-wdt"; |
| reg = <0 0x10007000 0 0x100>; |
| #reset-cells = <1>; |
| }; |
| |
| apmixedsys: syscon@1000c000 { |
| compatible = "mediatek,mt8192-apmixedsys", "syscon"; |
| reg = <0 0x1000c000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| systimer: timer@10017000 { |
| compatible = "mediatek,mt8192-timer", |
| "mediatek,mt6765-timer"; |
| reg = <0 0x10017000 0 0x1000>; |
| interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&clk13m>; |
| }; |
| |
| pwrap: pwrap@10026000 { |
| compatible = "mediatek,mt6873-pwrap"; |
| reg = <0 0x10026000 0 0x1000>; |
| reg-names = "pwrap"; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&infracfg CLK_INFRA_PMIC_AP>, |
| <&infracfg CLK_INFRA_PMIC_TMR>; |
| clock-names = "spi", "wrap"; |
| assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; |
| }; |
| |
| spmi: spmi@10027000 { |
| compatible = "mediatek,mt6873-spmi"; |
| reg = <0 0x10027000 0 0x000e00>, |
| <0 0x10029000 0 0x000100>; |
| reg-names = "pmif", "spmimst"; |
| clocks = <&infracfg CLK_INFRA_PMIC_AP>, |
| <&infracfg CLK_INFRA_PMIC_TMR>, |
| <&topckgen CLK_TOP_SPMI_MST_SEL>; |
| clock-names = "pmif_sys_ck", |
| "pmif_tmr_ck", |
| "spmimst_clk_mux"; |
| assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| }; |
| |
| gce: mailbox@10228000 { |
| compatible = "mediatek,mt8192-gce"; |
| reg = <0 0x10228000 0 0x4000>; |
| interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; |
| #mbox-cells = <3>; |
| clocks = <&infracfg CLK_INFRA_GCE>; |
| clock-names = "gce"; |
| }; |
| |
| scp_adsp: syscon@10720000 { |
| compatible = "mediatek,mt8192-scp_adsp", "syscon"; |
| reg = <0 0x10720000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| uart0: serial@11002000 { |
| compatible = "mediatek,mt8192-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11002000 0 0x1000>; |
| interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@11003000 { |
| compatible = "mediatek,mt8192-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11003000 0 0x1000>; |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| imp_iic_wrap_c: syscon@11007000 { |
| compatible = "mediatek,mt8192-imp_iic_wrap_c", "syscon"; |
| reg = <0 0x11007000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| spi0: spi@1100a000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x1100a000 0 0x1000>; |
| interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI0>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| lvts: lvts@1100b000 { |
| compatible = "mediatek,mt6873-lvts"; |
| #thermal-sensor-cells = <1>; |
| reg = <0 0x1100b000 0 0x1000>, |
| <0 0x11278000 0 0x1000>; |
| interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; |
| |
| clocks = <&infracfg CLK_INFRA_THERM>; |
| clock-names = "lvts_clk"; |
| |
| resets = <&infracfg_rst 0>, |
| <&infracfg_rst 1>; |
| |
| nvmem-cells = <&lvts_e_data1>; |
| nvmem-cell-names = "e_data1"; |
| }; |
| |
| svs: svs@1100b000 { |
| compatible = "mediatek,mt8192-svs"; |
| reg = <0 0x1100b000 0 0x1000>; |
| interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&infracfg CLK_INFRA_THERM>; |
| clock-names = "main"; |
| nvmem-cells = <&svs_calibration>, |
| <&lvts_e_data1>; |
| nvmem-cell-names = "svs-calibration-data", |
| "t-calibration-data"; |
| resets = <&infracfg_rst 4>; |
| reset-names = "svs_rst"; |
| }; |
| |
| pwm0: pwm@1100e000 { |
| compatible = "mediatek,mt8183-disp-pwm"; |
| reg = <0 0x1100e000 0 0x1000>; |
| interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; |
| #pwm-cells = <2>; |
| clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, |
| <&infracfg CLK_INFRA_DISP_PWM>; |
| clock-names = "main", "mm"; |
| }; |
| |
| spi1: spi@11010000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11010000 0 0x1000>; |
| interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI1>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@11012000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11012000 0 0x1000>; |
| interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI2>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@11013000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11013000 0 0x1000>; |
| interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI3>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@11018000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11018000 0 0x1000>; |
| interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI4>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@11019000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11019000 0 0x1000>; |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI5>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi6: spi@1101d000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x1101d000 0 0x1000>; |
| interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI6>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi7: spi@1101e000 { |
| compatible = "mediatek,mt8192-spi", |
| "mediatek,mt6765-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x1101e000 0 0x1000>; |
| interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI7>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| scp: scp@10500000 { |
| compatible = "mediatek,mt8192-scp"; |
| reg = <0 0x10500000 0 0x100000>, |
| <0 0x10700000 0 0x8000>, |
| <0 0x10720000 0 0xe0000>; |
| reg-names = "sram", "l1tcm", "cfg"; |
| interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&infracfg CLK_INFRA_SCPSYS>; |
| clock-names = "main"; |
| status = "disabled"; |
| }; |
| |
| xhci: xhci@11200000 { |
| compatible = "mediatek,mt8192-xhci", |
| "mediatek,mtk-xhci"; |
| reg = <0 0x11200000 0 0x1000>, |
| <0 0x11203e00 0 0x0100>; |
| reg-names = "mac", "ippc"; |
| interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; |
| interrupt-names = "host"; |
| phys = <&u2port0 PHY_TYPE_USB2>, |
| <&u3port0 PHY_TYPE_USB3>; |
| assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, |
| <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, |
| <&topckgen CLK_TOP_UNIVPLL_D5_D4>; |
| clocks = <&infracfg CLK_INFRA_SSUSB>, |
| <&infracfg CLK_INFRA_SSUSB_XHCI>, |
| <&apmixedsys CLK_APMIXED_USBPLL>; |
| clock-names = "sys_ck", "xhci_ck", "ref_ck"; |
| wakeup-source; |
| mediatek,syscon-wakeup = <&pericfg 0x420 102>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| }; |
| |
| audsys: syscon@11210000 { |
| compatible = "mediatek,mt8192-audsys", "syscon"; |
| reg = <0 0x11210000 0 0x2000>; |
| #clock-cells = <1>; |
| afe: mt8192-afe-pcm { |
| compatible = "mediatek,mt8192-audio"; |
| interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; |
| resets = <&watchdog 17>; |
| reset-names = "audiosys"; |
| mediatek,apmixedsys = <&apmixedsys>; |
| mediatek,infracfg = <&infracfg>; |
| mediatek,topckgen = <&topckgen>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; |
| clocks = <&audsys CLK_AUD_AFE>, |
| <&audsys CLK_AUD_DAC>, |
| <&audsys CLK_AUD_DAC_PREDIS>, |
| <&audsys CLK_AUD_ADC>, |
| <&audsys CLK_AUD_ADDA6_ADC>, |
| <&audsys CLK_AUD_22M>, |
| <&audsys CLK_AUD_24M>, |
| <&audsys CLK_AUD_APLL_TUNER>, |
| <&audsys CLK_AUD_APLL2_TUNER>, |
| <&audsys CLK_AUD_TDM>, |
| <&audsys CLK_AUD_TML>, |
| <&audsys CLK_AUD_NLE>, |
| <&audsys CLK_AUD_DAC_HIRES>, |
| <&audsys CLK_AUD_ADC_HIRES>, |
| <&audsys CLK_AUD_ADC_HIRES_TML>, |
| <&audsys CLK_AUD_ADDA6_ADC_HIRES>, |
| <&audsys CLK_AUD_3RD_DAC>, |
| <&audsys CLK_AUD_3RD_DAC_PREDIS>, |
| <&audsys CLK_AUD_3RD_DAC_TML>, |
| <&audsys CLK_AUD_3RD_DAC_HIRES>, |
| <&infracfg CLK_INFRA_AUDIO>, |
| <&infracfg CLK_INFRA_AUDIO_26M_B>, |
| <&topckgen CLK_TOP_AUDIO_SEL>, |
| <&topckgen CLK_TOP_AUD_INTBUS_SEL>, |
| <&topckgen CLK_TOP_MAINPLL_D4_D4>, |
| <&topckgen CLK_TOP_AUD_1_SEL>, |
| <&topckgen CLK_TOP_APLL1>, |
| <&topckgen CLK_TOP_AUD_2_SEL>, |
| <&topckgen CLK_TOP_APLL2>, |
| <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, |
| <&topckgen CLK_TOP_APLL1_D4>, |
| <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, |
| <&topckgen CLK_TOP_APLL2_D4>, |
| <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, |
| <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, |
| <&topckgen CLK_TOP_APLL12_DIV0>, |
| <&topckgen CLK_TOP_APLL12_DIV1>, |
| <&topckgen CLK_TOP_APLL12_DIV2>, |
| <&topckgen CLK_TOP_APLL12_DIV3>, |
| <&topckgen CLK_TOP_APLL12_DIV4>, |
| <&topckgen CLK_TOP_APLL12_DIVB>, |
| <&topckgen CLK_TOP_APLL12_DIV5>, |
| <&topckgen CLK_TOP_APLL12_DIV6>, |
| <&topckgen CLK_TOP_APLL12_DIV7>, |
| <&topckgen CLK_TOP_APLL12_DIV8>, |
| <&topckgen CLK_TOP_APLL12_DIV9>, |
| <&topckgen CLK_TOP_AUDIO_H_SEL>, |
| <&clk26m>; |
| clock-names = "aud_afe_clk", |
| "aud_dac_clk", |
| "aud_dac_predis_clk", |
| "aud_adc_clk", |
| "aud_adda6_adc_clk", |
| "aud_apll22m_clk", |
| "aud_apll24m_clk", |
| "aud_apll1_tuner_clk", |
| "aud_apll2_tuner_clk", |
| "aud_tdm_clk", |
| "aud_tml_clk", |
| "aud_nle", |
| "aud_dac_hires_clk", |
| "aud_adc_hires_clk", |
| "aud_adc_hires_tml", |
| "aud_adda6_adc_hires_clk", |
| "aud_3rd_dac_clk", |
| "aud_3rd_dac_predis_clk", |
| "aud_3rd_dac_tml", |
| "aud_3rd_dac_hires_clk", |
| "aud_infra_clk", |
| "aud_infra_26m_clk", |
| "top_mux_audio", |
| "top_mux_audio_int", |
| "top_mainpll_d4_d4", |
| "top_mux_aud_1", |
| "top_apll1_ck", |
| "top_mux_aud_2", |
| "top_apll2_ck", |
| "top_mux_aud_eng1", |
| "top_apll1_d4", |
| "top_mux_aud_eng2", |
| "top_apll2_d4", |
| "top_i2s0_m_sel", |
| "top_i2s1_m_sel", |
| "top_i2s2_m_sel", |
| "top_i2s3_m_sel", |
| "top_i2s4_m_sel", |
| "top_i2s5_m_sel", |
| "top_i2s6_m_sel", |
| "top_i2s7_m_sel", |
| "top_i2s8_m_sel", |
| "top_i2s9_m_sel", |
| "top_apll12_div0", |
| "top_apll12_div1", |
| "top_apll12_div2", |
| "top_apll12_div3", |
| "top_apll12_div4", |
| "top_apll12_divb", |
| "top_apll12_div5", |
| "top_apll12_div6", |
| "top_apll12_div7", |
| "top_apll12_div8", |
| "top_apll12_div9", |
| "top_mux_audio_h", |
| "top_clk26m_clk"; |
| }; |
| }; |
| |
| pcie: pcie@11230000 { |
| compatible = "mediatek,mt8192-pcie"; |
| device_type = "pci"; |
| reg = <0 0x11230000 0 0x2000>; |
| reg-names = "pcie-mac"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>, |
| <&infracfg CLK_INFRA_PCIE_TL_96M>, |
| <&infracfg CLK_INFRA_PCIE_TL_32K>, |
| <&infracfg CLK_INFRA_PCIE_PERI_26M>, |
| <&infracfg CLK_INFRA_PCIE_TOP_H_133M>, |
| <&infracfg CLK_INFRA_PCIE_PL_P_250M>; |
| clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", |
| "obff_ck0", "axi_ck0", "pipe_ck0"; |
| assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; |
| resets = <&infracfg_rst 2>, |
| <&infracfg_rst 3>; |
| reset-names = "phy", "mac"; |
| interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; |
| bus-range = <0x00 0xff>; |
| ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, |
| <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; |
| |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &pcie_intc0 0>, |
| <0 0 0 2 &pcie_intc0 1>, |
| <0 0 0 3 &pcie_intc0 2>, |
| <0 0 0 4 &pcie_intc0 3>; |
| pcie_intc0: interrupt-controller { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| nor_flash: spi@11234000 { |
| compatible = "mediatek,mt8192-nor"; |
| reg = <0 0x11234000 0 0xe0>; |
| interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_SFLASH_SEL>, |
| <&infracfg CLK_INFRA_FLASHIF_SFLASH>, |
| <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; |
| clock-names = "spi", "sf", "axi"; |
| assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; |
| assigned-clock-parents = <&clk26m>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| efuse: efuse@11c10000 { |
| compatible = "mediatek,efuse"; |
| reg = <0 0x11c10000 0 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| lvts_e_data1: data1 { |
| reg = <0x1C0 0x58>; |
| }; |
| |
| socinfo-data1@44 { |
| reg = <0x044 0x4>; |
| }; |
| |
| socinfo-data2@50 { |
| reg = <0x050 0x4>; |
| }; |
| |
| svs_calibration: calib@580 { |
| reg = <0x580 0x68>; |
| }; |
| }; |
| |
| i2c3: i2c3@11cb0000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11cb0000 0 0x1000>, |
| <0 0x10217300 0 0x80>; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| imp_iic_wrap_e: syscon@11cb1000 { |
| compatible = "mediatek,mt8192-imp_iic_wrap_e", "syscon"; |
| reg = <0 0x11cb1000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| i2c7: i2c7@11d00000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11d00000 0 0x1000>, |
| <0 0x10217600 0 0x180>; |
| interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c8: i2c8@11d01000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11d01000 0 0x1000>, |
| <0 0x10217780 0 0x180>; |
| interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c9: i2c9@11d02000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11d02000 0 0x1000>, |
| <0 0x10217900 0 0x180>; |
| interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| imp_iic_wrap_s: syscon@11d03000 { |
| compatible = "mediatek,mt8192-imp_iic_wrap_s", "syscon"; |
| reg = <0 0x11d03000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| i2c1: i2c1@11d20000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11d20000 0 0x1000>, |
| <0 0x10217100 0 0x80>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c2@11d21000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11d21000 0 0x1000>, |
| <0 0x10217180 0 0x180>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c4@11d22000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11d22000 0 0x1000>, |
| <0 0x10217380 0 0x180>; |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| imp_iic_wrap_ws: syscon@11d23000 { |
| compatible = "mediatek,mt8192-imp_iic_wrap_ws", "syscon"; |
| reg = <0 0x11d23000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| i2c5: i2c5@11e00000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11e00000 0 0x1000>, |
| <0 0x10217500 0 0x80>; |
| interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| imp_iic_wrap_w: syscon@11e01000 { |
| compatible = "mediatek,mt8192-imp_iic_wrap_w", "syscon"; |
| reg = <0 0x11e01000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| u3phy0: usb-phy@11e40000 { |
| compatible = "mediatek,mt8192-tphy", |
| "mediatek,generic-tphy-v2"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "okay"; |
| |
| u2port0: usb-phy@11e40000 { |
| reg = <0 0x11e40000 0 0x700>; |
| clocks = <&clk26m>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| status = "okay"; |
| }; |
| |
| u3port0: usb-phy@11e40700 { |
| reg = <0 0x11e40700 0 0x900>; |
| clocks = <&clk26m>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| status = "okay"; |
| }; |
| }; |
| |
| mipi_tx0: mipi-dphy@11e50000 { |
| compatible = "mediatek,mt8183-mipi-tx"; |
| reg = <0 0x11e50000 0 0x1000>; |
| clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; |
| clock-names = "ref_clk"; |
| #clock-cells = <0>; |
| #phy-cells = <0>; |
| clock-output-names = "mipi_tx0_pll"; |
| }; |
| |
| i2c0: i2c0@11f00000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11f00000 0 0x1000>, |
| <0 0x10217080 0 0x80>; |
| interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c6@11f01000 { |
| compatible = "mediatek,mt8192-i2c"; |
| reg = <0 0x11f01000 0 0x1000>, |
| <0 0x10217580 0 0x80>; |
| interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| imp_iic_wrap_n: syscon@11f02000 { |
| compatible = "mediatek,mt8192-imp_iic_wrap_n", "syscon"; |
| reg = <0 0x11f02000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| msdc_top: syscon@11f10000 { |
| compatible = "mediatek,mt8192-msdc_top", "syscon"; |
| reg = <0 0x11f10000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| mmc0: mmc@11f60000 { |
| compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; |
| reg = <0 0x11f60000 0 0x1000>, |
| <0 0x11f50000 0 0x1000>; |
| interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, |
| <&msdc_top CLK_MSDC_TOP_H_MST_0P>, |
| <&msdc_top CLK_MSDC_TOP_SRC_0P>, |
| <&msdc_top CLK_MSDC_TOP_P_CFG>, |
| <&msdc_top CLK_MSDC_TOP_AXI>, |
| <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>, |
| <&msdc_top CLK_MSDC_TOP_P_MSDC0>; |
| clock-names = "source", "hclk", "source_cg", "sys_cg", |
| "axi_cg", "ahb_cg", "pclk_cg"; |
| status = "disabled"; |
| }; |
| |
| mmc1: mmc@11f70000 { |
| compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; |
| reg = <0 0x11f70000 0 0x1000>, |
| <0 0x11c70000 0 0x1000>; |
| interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, |
| <&msdc_top CLK_MSDC_TOP_H_MST_1P>, |
| <&msdc_top CLK_MSDC_TOP_SRC_1P>, |
| <&msdc_top CLK_MSDC_TOP_P_CFG>, |
| <&msdc_top CLK_MSDC_TOP_AXI>, |
| <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>, |
| <&msdc_top CLK_MSDC_TOP_P_MSDC1>; |
| clock-names = "source", "hclk", "source_cg", "sys_cg", |
| "axi_cg", "ahb_cg", "pclk_cg"; |
| status = "disabled"; |
| }; |
| |
| gpu: mali@13000000 { |
| compatible = "mediatek,mt8192-mali", |
| "mediatek,mali", |
| "arm,mali-valhall"; |
| reg = <0 0x13000000 0 0x4000>; |
| interrupts = |
| <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>, |
| <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>, |
| <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>; |
| interrupt-names = "gpu", "mmu", "job"; |
| |
| /* |
| * Note: the properties below are not part of the |
| * upstream binding. |
| */ |
| clocks = |
| <&apmixedsys CLK_APMIXED_MFGPLL>, |
| <&topckgen CLK_TOP_MFG_PLL_SEL>, |
| <&topckgen CLK_TOP_MFG_REF_SEL>, |
| <&mfgcfg CLK_MFG_BG3D>; |
| clock-names = |
| "clk_main_parent", |
| "clk_mux", |
| "clk_sub_parent", |
| "subsys_mfg_cg"; |
| |
| power-domains = |
| <&spm MT8192_POWER_DOMAIN_MFG2>, |
| <&spm MT8192_POWER_DOMAIN_MFG3>, |
| <&spm MT8192_POWER_DOMAIN_MFG4>, |
| <&spm MT8192_POWER_DOMAIN_MFG5>, |
| <&spm MT8192_POWER_DOMAIN_MFG6>; |
| power-domain-names = "core0", |
| "core1", |
| "core2", |
| "core3", |
| "core4"; |
| #cooling-cells = <2>; |
| }; |
| |
| gpu_opp_table: opp_table0 { |
| /* |
| * Note: "operating-points-v2-mali" compatible and the |
| * opp-core-mask properties are not part of upstream |
| * binding. |
| */ |
| |
| compatible = "operating-points-v2", "operating-points-v2-mali"; |
| opp-shared; |
| |
| opp-358000000 { |
| opp-hz = /bits/ 64 <358000000>; |
| opp-hz-real = /bits/ 64 <358000000>, |
| /bits/ 64 <358000000>; |
| opp-microvolt = <606250>, |
| <750000>; |
| }; |
| |
| opp-399000000 { |
| opp-hz = /bits/ 64 <399000000>; |
| opp-hz-real = /bits/ 64 <399000000>, |
| /bits/ 64 <399000000>; |
| opp-microvolt = <618750>, |
| <750000>; |
| }; |
| |
| opp-440000000 { |
| opp-hz = /bits/ 64 <440000000>; |
| opp-hz-real = /bits/ 64 <440000000>, |
| /bits/ 64 <440000000>; |
| opp-microvolt = <631250>, |
| <750000>; |
| }; |
| |
| opp-482000000 { |
| opp-hz = /bits/ 64 <482000000>; |
| opp-hz-real = /bits/ 64 <482000000>, |
| /bits/ 64 <482000000>; |
| opp-microvolt = <643750>, |
| <750000>; |
| }; |
| |
| opp-523000000 { |
| opp-hz = /bits/ 64 <523000000>; |
| opp-hz-real = /bits/ 64 <523000000>, |
| /bits/ 64 <523000000>; |
| opp-microvolt = <656250>, |
| <750000>; |
| }; |
| |
| opp-564000000 { |
| opp-hz = /bits/ 64 <564000000>; |
| opp-hz-real = /bits/ 64 <564000000>, |
| /bits/ 64 <564000000>; |
| opp-microvolt = <668750>, |
| <750000>; |
| }; |
| |
| opp-605000000 { |
| opp-hz = /bits/ 64 <605000000>; |
| opp-hz-real = /bits/ 64 <605000000>, |
| /bits/ 64 <605000000>; |
| opp-microvolt = <681250>, |
| <750000>; |
| }; |
| |
| opp-647000000 { |
| opp-hz = /bits/ 64 <647000000>; |
| opp-hz-real = /bits/ 64 <647000000>, |
| /bits/ 64 <647000000>; |
| opp-microvolt = <693750>, |
| <750000>; |
| }; |
| |
| opp-688000000 { |
| opp-hz = /bits/ 64 <688000000>; |
| opp-hz-real = /bits/ 64 <688000000>, |
| /bits/ 64 <688000000>; |
| opp-microvolt = <706250>, |
| <750000>; |
| }; |
| |
| opp-724000000 { |
| opp-hz = /bits/ 64 <724000000>; |
| opp-hz-real = /bits/ 64 <724000000>, |
| /bits/ 64 <724000000>; |
| opp-microvolt = <725000>, |
| <750000>; |
| }; |
| |
| opp-748000000 { |
| opp-hz = /bits/ 64 <748000000>; |
| opp-hz-real = /bits/ 64 <748000000>, |
| /bits/ 64 <748000000>; |
| opp-microvolt = <737500>, |
| <750000>; |
| }; |
| |
| opp-772000000 { |
| opp-hz = /bits/ 64 <772000000>; |
| opp-hz-real = /bits/ 64 <772000000>, |
| /bits/ 64 <772000000>; |
| opp-microvolt = <750000>, |
| <750000>; |
| }; |
| |
| opp-795000000 { |
| opp-hz = /bits/ 64 <795000000>; |
| opp-hz-real = /bits/ 64 <795000000>, |
| /bits/ 64 <795000000>; |
| opp-microvolt = <762500>, |
| <762500>; |
| }; |
| |
| opp-819000000 { |
| opp-hz = /bits/ 64 <819000000>; |
| opp-hz-real = /bits/ 64 <819000000>, |
| /bits/ 64 <819000000>; |
| opp-microvolt = <775000>, |
| <775000>; |
| }; |
| |
| opp-843000000 { |
| opp-hz = /bits/ 64 <843000000>; |
| opp-hz-real = /bits/ 64 <843000000>, |
| /bits/ 64 <843000000>; |
| opp-microvolt = <787500>, |
| <787500>; |
| }; |
| |
| opp-866000000 { |
| opp-hz = /bits/ 64 <866000000>; |
| opp-hz-real = /bits/ 64 <866000000>, |
| /bits/ 64 <866000000>; |
| opp-microvolt = <800000>, |
| <800000>; |
| }; |
| }; |
| |
| mfgcfg: syscon@13fbf000 { |
| compatible = "mediatek,mt8192-mfgcfg", "syscon"; |
| reg = <0 0x13fbf000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| mmsys: syscon@14000000 { |
| compatible = "mediatek,mt8192-mmsys", "syscon"; |
| reg = <0 0x14000000 0 0x1000>; |
| mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>, |
| <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| mutex: mutex@14001000 { |
| compatible = "mediatek,mt8192-disp-mutex"; |
| reg = <0 0x14001000 0 0x1000>; |
| interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&mmsys CLK_MM_DISP_MUTEX0>; |
| mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, |
| <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; |
| }; |
| |
| smi_common: smi@14002000 { |
| compatible = "mediatek,mt8192-smi-common"; |
| reg = <0 0x14002000 0 0x1000>; |
| clocks = <&mmsys CLK_MM_SMI_COMMON>, |
| <&mmsys CLK_MM_SMI_INFRA>, |
| <&mmsys CLK_MM_SMI_GALS>, |
| <&mmsys CLK_MM_SMI_GALS>; |
| clock-names = "apb", "smi", "gals0", "gals1"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| }; |
| |
| larb0: larb@14003000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x14003000 0 0x1000>; |
| mediatek,larb-id = <0>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&clk26m>, <&clk26m>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| }; |
| |
| larb1: larb@14004000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x14004000 0 0x1000>; |
| mediatek,larb-id = <1>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&clk26m>, <&clk26m>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| }; |
| |
| ovl0: ovl@14005000 { |
| compatible = "mediatek,mt8192-disp-ovl"; |
| reg = <0 0x14005000 0 0x1000>; |
| interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&mmsys CLK_MM_DISP_OVL0>; |
| iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, |
| <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; |
| }; |
| |
| ovl_2l0: ovl@14006000 { |
| compatible = "mediatek,mt8192-disp-ovl-2l"; |
| reg = <0 0x14006000 0 0x1000>; |
| interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; |
| iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, |
| <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; |
| }; |
| |
| rdma0: rdma@14007000 { |
| compatible = "mediatek,mt8192-disp-rdma"; |
| reg = <0 0x14007000 0 0x1000>; |
| interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&mmsys CLK_MM_DISP_RDMA0>; |
| iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; |
| mediatek,larb = <&larb0>; |
| mediatek,rdma-fifo-size = <5120>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; |
| }; |
| |
| color0: color@14009000 { |
| compatible = "mediatek,mt8192-disp-color", |
| "mediatek,mt8173-disp-color"; |
| reg = <0 0x14009000 0 0x1000>; |
| interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_COLOR0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; |
| }; |
| |
| ccorr0: ccorr@1400a000 { |
| compatible = "mediatek,mt8192-disp-ccorr"; |
| reg = <0 0x1400a000 0 0x1000>; |
| interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_CCORR0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; |
| }; |
| |
| aal0: aal@1400b000 { |
| compatible = "mediatek,mt8192-disp-aal"; |
| reg = <0 0x1400b000 0 0x1000>; |
| interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_AAL0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; |
| }; |
| |
| gamma0: gamma@1400c000 { |
| compatible = "mediatek,mt8192-disp-gamma", |
| "mediatek,mt8183-disp-gamma"; |
| reg = <0 0x1400c000 0 0x1000>; |
| interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_GAMMA0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; |
| }; |
| |
| postmask0: postmask@1400d000 { |
| compatible = "mediatek,mt8192-disp-postmask"; |
| reg = <0 0x1400d000 0 0x1000>; |
| interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; |
| iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; |
| }; |
| |
| dither0: dither@1400e000 { |
| compatible = "mediatek,mt8192-disp-dither", |
| "mediatek,mt8183-disp-dither"; |
| reg = <0 0x1400e000 0 0x1000>; |
| interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_DITHER0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; |
| }; |
| |
| dsi0: dsi@14010000 { |
| compatible = "mediatek,mt8183-dsi"; |
| reg = <0 0x14010000 0 0x1000>; |
| interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; |
| mediatek,syscon-dsi = <&mmsys 0x140>; |
| clocks = <&mmsys CLK_MM_DSI0>, |
| <&mmsys CLK_MM_DSI_DSI0>, |
| <&mipi_tx0>; |
| clock-names = "engine", "digital", "hs"; |
| phys = <&mipi_tx0>; |
| phy-names = "dphy"; |
| }; |
| |
| ovl_2l2: ovl@14014000 { |
| compatible = "mediatek,mt8192-disp-ovl-2l"; |
| reg = <0 0x14014000 0 0x1000>; |
| interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; |
| iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, |
| <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; |
| }; |
| |
| rdma4: rdma@14015000 { |
| compatible = "mediatek,mt8192-disp-rdma"; |
| reg = <0 0x14015000 0 0x1000>; |
| interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| clocks = <&mmsys CLK_MM_DISP_RDMA4>; |
| iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; |
| mediatek,rdma-fifo-size = <2048>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; |
| }; |
| |
| dpi0: dpi@14016000 { |
| compatible = "mediatek,mt8192-dpi"; |
| reg = <0 0x14016000 0 0x1000>; |
| interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&mmsys CLK_MM_DPI_DPI0>, |
| <&mmsys CLK_MM_DISP_DPI0>, |
| <&apmixedsys CLK_APMIXED_TVDPLL>; |
| clock-names = "pixel", "engine", "pll"; |
| }; |
| |
| iommu0: m4u@1401d000 { |
| compatible = "mediatek,mt8192-m4u"; |
| reg = <0 0x1401d000 0 0x1000>; |
| mediatek,larbs = <&larb0 &larb1 &larb2 |
| &larb4 &larb5 &larb7 |
| &larb9 &larb11 &larb13 |
| &larb14 &larb16 &larb17 |
| &larb18 &larb19 &larb20>; |
| interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&mmsys CLK_MM_SMI_IOMMU>; |
| clock-names = "bclk"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; |
| #iommu-cells = <1>; |
| }; |
| |
| imgsys: syscon@15020000 { |
| compatible = "mediatek,mt8192-imgsys", "syscon"; |
| reg = <0 0x15020000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb9: larb@1502e000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1502e000 0 0x1000>; |
| mediatek,larb-id = <9>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&imgsys CLK_IMG_LARB9>, |
| <&imgsys CLK_IMG_LARB9>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; |
| }; |
| |
| imgsys2: syscon@15820000 { |
| compatible = "mediatek,mt8192-imgsys2", "syscon"; |
| reg = <0 0x15820000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb11: larb@1582e000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1582e000 0 0x1000>; |
| mediatek,larb-id = <11>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&imgsys2 CLK_IMG2_LARB11>, |
| <&imgsys2 CLK_IMG2_LARB11>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; |
| }; |
| |
| vcodec_dec: vcodec_dec@16000000 { |
| compatible = "mediatek,mt8192-vcodec-dec"; |
| reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ |
| mediatek,scp = <&scp>; |
| iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; |
| }; |
| |
| vcodec_lat: vcodec_lat@0x16010000 { |
| compatible = "mediatek,mtk-vcodec-lat"; |
| reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */ |
| interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>; |
| iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, |
| <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, |
| <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, |
| <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, |
| <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, |
| <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, |
| <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, |
| <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; |
| clocks = <&topckgen CLK_TOP_VDEC_SEL>, |
| <&vdecsys_soc CLK_VDEC_SOC_VDEC>, |
| <&vdecsys_soc CLK_VDEC_SOC_LAT>, |
| <&vdecsys_soc CLK_VDEC_SOC_LARB1>, |
| <&topckgen CLK_TOP_MAINPLL_D4>; |
| clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec", "vdec-top"; |
| assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; |
| }; |
| |
| vcodec_core: vcodec_core@0x16025000 { |
| compatible = "mediatek,mtk-vcodec-core"; |
| reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */ |
| interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>; |
| iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, |
| <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, |
| <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, |
| <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, |
| <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, |
| <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, |
| <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, |
| <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, |
| <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, |
| <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, |
| <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; |
| clocks = <&topckgen CLK_TOP_VDEC_SEL>, |
| <&vdecsys CLK_VDEC_VDEC>, |
| <&vdecsys CLK_VDEC_LAT>, |
| <&vdecsys CLK_VDEC_LARB1>, |
| <&topckgen CLK_TOP_MAINPLL_D4>; |
| clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", "vdec-vdec", "vdec-top"; |
| assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; |
| }; |
| |
| larb5: larb@1600d000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1600d000 0 0x1000>; |
| mediatek,larb-id = <5>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, |
| <&vdecsys_soc CLK_VDEC_SOC_LARB1>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; |
| }; |
| |
| vdecsys_soc: syscon@1600f000 { |
| compatible = "mediatek,mt8192-vdecsys_soc", "syscon"; |
| reg = <0 0x1600f000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb4: larb@1602e000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1602e000 0 0x1000>; |
| mediatek,larb-id = <4>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, |
| <&vdecsys CLK_VDEC_SOC_LARB1>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; |
| }; |
| |
| vdecsys: syscon@1602f000 { |
| compatible = "mediatek,mt8192-vdecsys", "syscon"; |
| reg = <0 0x1602f000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| vencsys: syscon@17000000 { |
| compatible = "mediatek,mt8192-vencsys", "syscon"; |
| reg = <0 0x17000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb7: larb@17010000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x17010000 0 0x1000>; |
| mediatek,larb-id = <7>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&vencsys CLK_VENC_SET0_LARB>, |
| <&vencsys CLK_VENC_SET1_VENC>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; |
| }; |
| |
| vcodec_enc: vcodec@0x17020000 { |
| compatible = "mediatek,mt8192-vcodec-enc"; |
| reg = <0 0x17020000 0 0x2000>; |
| iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, |
| <&iommu0 M4U_PORT_L7_VENC_REC>, |
| <&iommu0 M4U_PORT_L7_VENC_BSDMA>, |
| <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, |
| <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, |
| <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, |
| <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, |
| <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, |
| <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, |
| <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, |
| <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; |
| interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; |
| mediatek,scp = <&scp>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; |
| clocks = <&vencsys CLK_VENC_SET1_VENC>; |
| clock-names = "venc-set1"; |
| assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; |
| }; |
| |
| camsys: syscon@1a000000 { |
| compatible = "mediatek,mt8192-camsys", "syscon"; |
| reg = <0 0x1a000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb13: larb@1a001000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1a001000 0 0x1000>; |
| mediatek,larb-id = <13>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&camsys CLK_CAM_CAM>, |
| <&camsys CLK_CAM_LARB13>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; |
| }; |
| |
| larb14: larb@1a002000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1a002000 0 0x1000>; |
| mediatek,larb-id = <14>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&camsys CLK_CAM_CAM>, |
| <&camsys CLK_CAM_LARB14>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; |
| }; |
| |
| larb16: larb@1a00f000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1a00f000 0 0x1000>; |
| mediatek,larb-id = <16>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, |
| <&camsys_rawa CLK_CAM_RAWA_LARBX>; |
| clock-names = "apb", "smi"; |
| mediatek,smi-id = <16>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; |
| }; |
| |
| larb17: larb@1a010000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1a010000 0 0x1000>; |
| mediatek,larb-id = <17>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, |
| <&camsys_rawb CLK_CAM_RAWB_LARBX>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; |
| }; |
| |
| larb18: larb@1a011000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1a011000 0 0x1000>; |
| mediatek,larb-id = <18>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, |
| <&camsys_rawc CLK_CAM_RAWC_CAM>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; |
| }; |
| |
| camsys_rawa: syscon@1a04f000 { |
| compatible = "mediatek,mt8192-camsys_rawa", "syscon"; |
| reg = <0 0x1a04f000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| camsys_rawb: syscon@1a06f000 { |
| compatible = "mediatek,mt8192-camsys_rawb", "syscon"; |
| reg = <0 0x1a06f000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| camsys_rawc: syscon@1a08f000 { |
| compatible = "mediatek,mt8192-camsys_rawc", "syscon"; |
| reg = <0 0x1a08f000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| ipesys: syscon@1b000000 { |
| compatible = "mediatek,mt8192-ipesys", "syscon"; |
| reg = <0 0x1b000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb20: larb@1b00f000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1b00f000 0 0x1000>; |
| mediatek,larb-id = <20>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, |
| <&ipesys CLK_IPE_LARB20>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; |
| }; |
| |
| larb19: larb@1b10f000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1b10f000 0 0x1000>; |
| mediatek,larb-id = <19>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, |
| <&ipesys CLK_IPE_LARB19>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; |
| }; |
| |
| mdpsys: syscon@1f000000 { |
| compatible = "mediatek,mt8192-mdpsys", "syscon"; |
| reg = <0 0x1f000000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| mdp_mutex: mdp_mutex@1f001000 { |
| compatible = "mediatek,mdp_mutex"; |
| reg = <0 0x1f001000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0x1000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_MUTEX0>; |
| clock-names = "MDP_MUTEX0"; |
| }; |
| |
| mdp_rdma0: mdp_rdma0@1f003000 { |
| compatible = "mediatek,mt8192-mdp-rdma", |
| "mediatek,mt8192-mdp3"; |
| mediatek,scp = <&scp>; |
| mediatek,mdp-id = <0>; |
| mdp-comps = "mediatek,mt8192-mdp-dl", "mediatek,mt8192-mdp-dl"; |
| mdp-comp-ids = <0 1>; |
| reg = <0 0x1f003000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0x3000 0x1000>; |
| mediatek,larb = <&larb2>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| clocks = <&mdpsys CLK_MDP_RDMA0>; |
| clock-names = "MDP_RDMA0"; |
| iommus = <&iommu0 M4U_PORT_L2_MDP_RDMA0>; |
| mediatek,mmsys = <&mdpsys>; |
| mediatek,mm-mutex = <&mdp_mutex>; |
| mediatek,imgsys = <&imgsys>; |
| mediatek,mailbox-gce = <&gce>; |
| mboxes = <&gce 19 CMDQ_THR_PRIO_1 0>, |
| <&gce 20 CMDQ_THR_PRIO_1 0>, |
| <&gce 21 CMDQ_THR_PRIO_1 0>, |
| <&gce 22 CMDQ_THR_PRIO_1 0>; |
| mdp_rdma1 = <&mdp_rdma1>; |
| mdp_rsz0 = <&mdp_rsz0>; |
| mdp_rsz1 = <&mdp_rsz1>; |
| mdp_wrot0 = <&mdp_wrot0>; |
| mdp_wrot1 = <&mdp_wrot1>; |
| mdp_tdshp0 = <&mdp_tdshp0>; |
| mdp_tdshp1 = <&mdp_tdshp1>; |
| mdp_aal0 = <&mdp_aal0>; |
| mdp_aal1 = <&mdp_aal1>; |
| mdp_color0 = <&mdp_color0>; |
| mdp_color1 = <&mdp_color1>; |
| mdp_hdr0 = <&mdp_hdr0>; |
| mdp_hdr1 = <&mdp_hdr1>; |
| mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, |
| <CMDQ_EVENT_MDP_RDMA1_SOF>, |
| <CMDQ_EVENT_MDP_AAL0_SOF>, |
| <CMDQ_EVENT_MDP_AAL1_SOF>, |
| <CMDQ_EVENT_MDP_HDR0_SOF>, |
| <CMDQ_EVENT_MDP_HDR1_SOF>, |
| <CMDQ_EVENT_MDP_RSZ0_SOF>, |
| <CMDQ_EVENT_MDP_RSZ1_SOF>, |
| <CMDQ_EVENT_MDP_WROT0_SOF>, |
| <CMDQ_EVENT_MDP_WROT1_SOF>, |
| <CMDQ_EVENT_MDP_TDSHP0_SOF>, |
| <CMDQ_EVENT_MDP_TDSHP1_SOF>, |
| <CMDQ_EVENT_IMG_DL_RELAY0_SOF>, |
| <CMDQ_EVENT_IMG_DL_RELAY1_SOF>, |
| <CMDQ_EVENT_MDP_COLOR0_SOF>, |
| <CMDQ_EVENT_MDP_COLOR1_SOF>, |
| <CMDQ_EVENT_MDP_WROT1_FRAME_DONE>, |
| <CMDQ_EVENT_MDP_WROT0_FRAME_DONE>, |
| <CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE>, |
| <CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE>, |
| <CMDQ_EVENT_MDP_RSZ1_FRAME_DONE >, |
| <CMDQ_EVENT_MDP_RSZ0_FRAME_DONE >, |
| <CMDQ_EVENT_MDP_RDMA1_FRAME_DONE>, |
| <CMDQ_EVENT_MDP_RDMA0_FRAME_DONE>, |
| <CMDQ_EVENT_MDP_HDR1_FRAME_DONE>, |
| <CMDQ_EVENT_MDP_HDR0_FRAME_DONE>, |
| <CMDQ_EVENT_MDP_COLOR1_FRAME_DONE>, |
| <CMDQ_EVENT_MDP_COLOR0_FRAME_DONE>, |
| <CMDQ_EVENT_MDP_AAL1_FRAME_DONE>, |
| <CMDQ_EVENT_MDP_AAL0_FRAME_DONE>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14>, |
| <CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15>, |
| <CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_EVENT>, |
| <CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_EVENT>, |
| <CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_EVENT>, |
| <CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_EVENT>; |
| }; |
| |
| mdp_rdma1: mdp_rdma1@1f004000 { |
| compatible = "mediatek,mt8192-mdp-rdma"; |
| mediatek,mdp-id = <1>; |
| reg = <0 0x1f004000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0x4000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_RDMA1>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| iommus = <&iommu0 M4U_PORT_L2_MDP_RDMA1>; |
| }; |
| |
| mdp_aal0: mdp_aal0@1f005000 { |
| compatible = "mediatek,mt8192-mdp-aal"; |
| mediatek,mdp-id = <0>; |
| reg = <0 0x1f005000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0x5000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_AAL0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| }; |
| |
| mdp_aal1: mdp_aal1@1f006000 { |
| compatible = "mediatek,mt8192-mdp-aal"; |
| mediatek,mdp-id = <1>; |
| reg = <0 0x1f006000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0x6000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_AAL1>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| }; |
| |
| mdp_hdr0: mdp_hdr0@1f007000 { |
| compatible = "mediatek,mt8192-mdp-hdr"; |
| mediatek,mdp-id = <0>; |
| reg = <0 0x1f007000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0x7000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_HDR0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| }; |
| |
| mdp_hdr1: mdp_hdr1@1f008000 { |
| compatible = "mediatek,mt8192-mdp-hdr"; |
| mediatek,mdp-id = <1>; |
| reg = <0 0x1f008000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0x8000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_HDR1>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| }; |
| |
| mdp_rsz0: mdp_rsz0@1f009000 { |
| compatible = "mediatek,mt8192-mdp-rsz"; |
| mediatek,mdp-id = <0>; |
| reg = <0 0x1f009000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0x9000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_RSZ0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| }; |
| |
| mdp_rsz1: mdp_rsz1@1f00a000 { |
| compatible = "mediatek,mt8192-mdp-rsz"; |
| mediatek,mdp-id = <1>; |
| reg = <0 0x1f00a000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0xa000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_RSZ1>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| }; |
| |
| mdp_wrot0: mdp_wrot0@1f00b000 { |
| compatible = "mediatek,mt8192-mdp-wrot"; |
| mediatek,mdp-id = <0>; |
| reg = <0 0x1f00b000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0xb000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_WROT0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| iommus = <&iommu0 M4U_PORT_L2_MDP_WROT0>; |
| }; |
| |
| mdp_wrot1: mdp_wrot1@1f00c000 { |
| compatible = "mediatek,mt8192-mdp-wrot"; |
| mediatek,mdp-id = <1>; |
| reg = <0 0x1f00c000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0xc000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_WROT1>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| iommus = <&iommu0 M4U_PORT_L2_MDP_WROT1>; |
| }; |
| |
| mdp_tdshp0: mdp_tdshp0@1f00d000 { |
| compatible = "mediatek,mt8192-mdp-tdshp"; |
| mediatek,mdp-id = <0>; |
| reg = <0 0x1f00d000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0xd000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_TDSHP0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| }; |
| |
| mdp_tdshp1: mdp_tdshp1@1f00e000 { |
| compatible = "mediatek,mt8192-mdp-tdshp"; |
| mediatek,mdp-id = <1>; |
| reg = <0 0x1f00e000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0xe000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_TDSHP1>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| }; |
| |
| mdp_color0: mdp_color0@1f00f000 { |
| compatible = "mediatek,mt8192-mdp-color"; |
| mediatek,mdp-id = <0>; |
| reg = <0 0x1f00f000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f000 0xf000 0x1000>; |
| clocks = <&mdpsys CLK_MDP_COLOR0>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| }; |
| |
| mdp_color1: mdp_color1@1f010000 { |
| compatible = "mediatek,mt8192-mdp-color"; |
| mediatek,mdp-id = <1>; |
| reg = <0 0x1f010000 0 0x1000>; |
| mediatek,gce-client-reg = <&gce 0x1f010 0 0x1000>; |
| clocks = <&mdpsys CLK_MDP_COLOR1>; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| mediatek,larb = <&larb2>; |
| }; |
| |
| larb2: larb@1f002000 { |
| compatible = "mediatek,mt8192-smi-larb"; |
| reg = <0 0x1f002000 0 0x1000>; |
| mediatek,larb-id = <2>; |
| mediatek,smi = <&smi_common>; |
| clocks = <&mdpsys CLK_MDP_SMI0>, |
| <&mdpsys CLK_MDP_SMI0>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; |
| }; |
| }; |
| }; |
