arch/arm/boot/dts/sun8i-v3s.dtsi - third_party/linux - Git at Google

 /*
  * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
  * licensing only applies to this file, and not this project as a
  * whole.
  *
  *  a) This file is free software; you can redistribute it and/or
  *     modify it under the terms of the GNU General Public License as
  *     published by the Free Software Foundation; either version 2 of the
  *     License, or (at your option) any later version.
  *
  *     This file is distributed in the hope that it will be useful,
  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
  * Or, alternatively,
  *
  *  b) Permission is hereby granted, free of charge, to any person
  *     obtaining a copy of this software and associated documentation
  *     files (the "Software"), to deal in the Software without
  *     restriction, including without limitation the rights to use,
  *     copy, modify, merge, publish, distribute, sublicense, and/or
  *     sell copies of the Software, and to permit persons to whom the
  *     Software is furnished to do so, subject to the following
  *     conditions:
  *
  *     The above copyright notice and this permission notice shall be
  *     included in all copies or substantial portions of the Software.
  *
  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
  */

 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
 #include <dt-bindings/reset/sun8i-v3s-ccu.h>

 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
 	interrupt-parent = <&gic>;

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		cpu@0 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0>;
 			clocks = <&ccu CLK_CPU>;
 		};
 	};

 	de: display-engine {
 		compatible = "allwinner,sun8i-v3s-display-engine";
 		allwinner,pipelines = <&mixer0>;
 		status = "disabled";
 	};

 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};

 	clocks {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;

 		osc24M: osc24M_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <24000000>;
 			clock-output-names = "osc24M";
 		};

 		osc32k: osc32k_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <32768>;
 			clock-output-names = "osc32k";
 		};
 	};

 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;

 		display_clocks: clock@1000000 {
 			compatible = "allwinner,sun8i-v3s-de2-clk";
 			reg = <0x01000000 0x100000>;
 			clocks = <&ccu CLK_DE>,
 				 <&ccu CLK_BUS_DE>;
 			clock-names = "mod",
 				      "bus";
 			resets = <&ccu RST_BUS_DE>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};

 		mixer0: mixer@1100000 {
 			compatible = "allwinner,sun8i-v3s-de2-mixer";
 			reg = <0x01100000 0x100000>;
 			clocks = <&display_clocks 0>,
 				 <&display_clocks 6>;
 			clock-names = "bus",
 				      "mod";
 			resets = <&display_clocks 0>;
 			assigned-clocks = <&display_clocks 6>;
 			assigned-clock-rates = <150000000>;

 			ports {
 				#address-cells = <1>;
 				#size-cells = <0>;

 				mixer0_out: port@1 {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					reg = <1>;

 					mixer0_out_tcon0: endpoint@0 {
 						reg = <0>;
 						remote-endpoint = <&tcon0_in_mixer0>;
 					};
 				};
 			};
 		};

 		tcon0: lcd-controller@1c0c000 {
 			compatible = "allwinner,sun8i-v3s-tcon";
 			reg = <0x01c0c000 0x1000>;
 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_TCON0>,
 				 <&ccu CLK_TCON0>;
 			clock-names = "ahb",
 				      "tcon-ch0";
 			clock-output-names = "tcon-pixel-clock";
 			resets = <&ccu RST_BUS_TCON0>;
 			reset-names = "lcd";
 			status = "disabled";

 			ports {
 				#address-cells = <1>;
 				#size-cells = <0>;

 				tcon0_in: port@0 {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					reg = <0>;

 					tcon0_in_mixer0: endpoint@0 {
 						reg = <0>;
 						remote-endpoint = <&mixer0_out_tcon0>;
 					};
 				};

 				tcon0_out: port@1 {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					reg = <1>;
 				};
 			};
 		};


 		mmc0: mmc@1c0f000 {
 			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c0f000 0x1000>;
 			clocks = <&ccu CLK_BUS_MMC0>,
 				 <&ccu CLK_MMC0>,
 				 <&ccu CLK_MMC0_OUTPUT>,
 				 <&ccu CLK_MMC0_SAMPLE>;
 			clock-names = "ahb",
 				      "mmc",
 				      "output",
 				      "sample";
 			resets = <&ccu RST_BUS_MMC0>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

 		mmc1: mmc@1c10000 {
 			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c10000 0x1000>;
 			clocks = <&ccu CLK_BUS_MMC1>,
 				 <&ccu CLK_MMC1>,
 				 <&ccu CLK_MMC1_OUTPUT>,
 				 <&ccu CLK_MMC1_SAMPLE>;
 			clock-names = "ahb",
 				      "mmc",
 				      "output",
 				      "sample";
 			resets = <&ccu RST_BUS_MMC1>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&mmc1_pins>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

 		mmc2: mmc@1c11000 {
 			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c11000 0x1000>;
 			clocks = <&ccu CLK_BUS_MMC2>,
 				 <&ccu CLK_MMC2>,
 				 <&ccu CLK_MMC2_OUTPUT>,
 				 <&ccu CLK_MMC2_SAMPLE>;
 			clock-names = "ahb",
 				      "mmc",
 				      "output",
 				      "sample";
 			resets = <&ccu RST_BUS_MMC2>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

 		usb_otg: usb@1c19000 {
 			compatible = "allwinner,sun8i-h3-musb";
 			reg = <0x01c19000 0x0400>;
 			clocks = <&ccu CLK_BUS_OTG>;
 			resets = <&ccu RST_BUS_OTG>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mc";
 			phys = <&usbphy 0>;
 			phy-names = "usb";
 			extcon = <&usbphy 0>;
 			status = "disabled";
 		};

 		usbphy: phy@1c19400 {
 			compatible = "allwinner,sun8i-v3s-usb-phy";
 			reg = <0x01c19400 0x2c>,
 			      <0x01c1a800 0x4>;
 			reg-names = "phy_ctrl",
 				    "pmu0";
 			clocks = <&ccu CLK_USB_PHY0>;
 			clock-names = "usb0_phy";
 			resets = <&ccu RST_USB_PHY0>;
 			reset-names = "usb0_reset";
 			status = "disabled";
 			#phy-cells = <1>;
 		};

 		ccu: clock@1c20000 {
 			compatible = "allwinner,sun8i-v3s-ccu";
 			reg = <0x01c20000 0x400>;
 			clocks = <&osc24M>, <&osc32k>;
 			clock-names = "hosc", "losc";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};

 		rtc: rtc@1c20400 {
 			compatible = "allwinner,sun6i-a31-rtc";
 			reg = <0x01c20400 0x54>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};

 		pio: pinctrl@1c20800 {
 			compatible = "allwinner,sun8i-v3s-pinctrl";
 			reg = <0x01c20800 0x400>;
 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			#gpio-cells = <3>;
 			interrupt-controller;
 			#interrupt-cells = <3>;

 			i2c0_pins: i2c0 {
 				pins = "PB6", "PB7";
 				function = "i2c0";
 			};

 			uart0_pins_a: uart0@0 {
 				pins = "PB8", "PB9";
 				function = "uart0";
 			};

 			mmc0_pins_a: mmc0@0 {
 				pins = "PF0", "PF1", "PF2", "PF3",
 				       "PF4", "PF5";
 				function = "mmc0";
 				drive-strength = <30>;
 				bias-pull-up;
 			};

 			mmc1_pins: mmc1 {
 				pins = "PG0", "PG1", "PG2", "PG3",
 				       "PG4", "PG5";
 				function = "mmc1";
 				drive-strength = <30>;
 				bias-pull-up;
 			};

 			spi0_pins: spi0 {
 				pins = "PC0", "PC1", "PC2", "PC3";
 				function = "spi0";
 			};
 		};

 		timer@1c20c00 {
 			compatible = "allwinner,sun4i-a10-timer";
 			reg = <0x01c20c00 0xa0>;
 			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&osc24M>;
 		};

 		wdt0: watchdog@1c20ca0 {
 			compatible = "allwinner,sun6i-a31-wdt";
 			reg = <0x01c20ca0 0x20>;
 			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 		};

 		lradc: lradc@1c22800 {
 			compatible = "allwinner,sun4i-a10-lradc-keys";
 			reg = <0x01c22800 0x400>;
 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};

 		uart0: serial@1c28000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&ccu CLK_BUS_UART0>;
 			resets = <&ccu RST_BUS_UART0>;
 			status = "disabled";
 		};

 		uart1: serial@1c28400 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28400 0x400>;
 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&ccu CLK_BUS_UART1>;
 			resets = <&ccu RST_BUS_UART1>;
 			status = "disabled";
 		};

 		uart2: serial@1c28800 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28800 0x400>;
 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&ccu CLK_BUS_UART2>;
 			resets = <&ccu RST_BUS_UART2>;
 			status = "disabled";
 		};

 		i2c0: i2c@1c2ac00 {
 			compatible = "allwinner,sun6i-a31-i2c";
 			reg = <0x01c2ac00 0x400>;
 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C0>;
 			resets = <&ccu RST_BUS_I2C0>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&i2c0_pins>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

 		i2c1: i2c@1c2b000 {
 			compatible = "allwinner,sun6i-a31-i2c";
 			reg = <0x01c2b000 0x400>;
 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C1>;
 			resets = <&ccu RST_BUS_I2C1>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

 		spi0: spi@1c68000 {
 			compatible = "allwinner,sun8i-h3-spi";
 			reg = <0x01c68000 0x1000>;
 			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 			clock-names = "ahb", "mod";
 			pinctrl-names = "default";
 			pinctrl-0 = <&spi0_pins>;
 			resets = <&ccu RST_BUS_SPI0>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};

 		gic: interrupt-controller@1c81000 {
 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 			reg = <0x01c81000 0x1000>,
 			      <0x01c82000 0x1000>,
 			      <0x01c84000 0x2000>,
 			      <0x01c86000 0x2000>;
 			interrupt-controller;
 			#interrupt-cells = <3>;
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 	};
 };
	/*
	* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/sun8i-v3s-ccu.h>
	#include <dt-bindings/reset/sun8i-v3s-ccu.h>

	/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,cortex-a7";
	device_type = "cpu";
	reg = <0>;
	clocks = <&ccu CLK_CPU>;
	};
	};

	de: display-engine {
	compatible = "allwinner,sun8i-v3s-display-engine";
	allwinner,pipelines = <&mixer0>;
	status = "disabled";
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	osc24M: osc24M_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <24000000>;
	clock-output-names = "osc24M";
	};

	osc32k: osc32k_clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <32768>;
	clock-output-names = "osc32k";
	};
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	display_clocks: clock@1000000 {
	compatible = "allwinner,sun8i-v3s-de2-clk";
	reg = <0x01000000 0x100000>;
	clocks = <&ccu CLK_DE>,
	<&ccu CLK_BUS_DE>;
	clock-names = "mod",
	"bus";
	resets = <&ccu RST_BUS_DE>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	mixer0: mixer@1100000 {
	compatible = "allwinner,sun8i-v3s-de2-mixer";
	reg = <0x01100000 0x100000>;
	clocks = <&display_clocks 0>,
	<&display_clocks 6>;
	clock-names = "bus",
	"mod";
	resets = <&display_clocks 0>;
	assigned-clocks = <&display_clocks 6>;
	assigned-clock-rates = <150000000>;

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	mixer0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;

	mixer0_out_tcon0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&tcon0_in_mixer0>;
	};
	};
	};
	};

	tcon0: lcd-controller@1c0c000 {
	compatible = "allwinner,sun8i-v3s-tcon";
	reg = <0x01c0c000 0x1000>;
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_TCON0>,
	<&ccu CLK_TCON0>;
	clock-names = "ahb",
	"tcon-ch0";
	clock-output-names = "tcon-pixel-clock";
	resets = <&ccu RST_BUS_TCON0>;
	reset-names = "lcd";
	status = "disabled";

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	tcon0_in: port@0 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0>;

	tcon0_in_mixer0: endpoint@0 {
	reg = <0>;
	remote-endpoint = <&mixer0_out_tcon0>;
	};
	};

	tcon0_out: port@1 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <1>;
	};
	};
	};


	mmc0: mmc@1c0f000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c0f000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC0>,
	<&ccu CLK_MMC0>,
	<&ccu CLK_MMC0_OUTPUT>,
	<&ccu CLK_MMC0_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_BUS_MMC0>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc1: mmc@1c10000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c10000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC1>,
	<&ccu CLK_MMC1>,
	<&ccu CLK_MMC1_OUTPUT>,
	<&ccu CLK_MMC1_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_BUS_MMC1>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	mmc2: mmc@1c11000 {
	compatible = "allwinner,sun7i-a20-mmc";
	reg = <0x01c11000 0x1000>;
	clocks = <&ccu CLK_BUS_MMC2>,
	<&ccu CLK_MMC2>,
	<&ccu CLK_MMC2_OUTPUT>,
	<&ccu CLK_MMC2_SAMPLE>;
	clock-names = "ahb",
	"mmc",
	"output",
	"sample";
	resets = <&ccu RST_BUS_MMC2>;
	reset-names = "ahb";
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	usb_otg: usb@1c19000 {
	compatible = "allwinner,sun8i-h3-musb";
	reg = <0x01c19000 0x0400>;
	clocks = <&ccu CLK_BUS_OTG>;
	resets = <&ccu RST_BUS_OTG>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mc";
	phys = <&usbphy 0>;
	phy-names = "usb";
	extcon = <&usbphy 0>;
	status = "disabled";
	};

	usbphy: phy@1c19400 {
	compatible = "allwinner,sun8i-v3s-usb-phy";
	reg = <0x01c19400 0x2c>,
	<0x01c1a800 0x4>;
	reg-names = "phy_ctrl",
	"pmu0";
	clocks = <&ccu CLK_USB_PHY0>;
	clock-names = "usb0_phy";
	resets = <&ccu RST_USB_PHY0>;
	reset-names = "usb0_reset";
	status = "disabled";
	#phy-cells = <1>;
	};

	ccu: clock@1c20000 {
	compatible = "allwinner,sun8i-v3s-ccu";
	reg = <0x01c20000 0x400>;
	clocks = <&osc24M>, <&osc32k>;
	clock-names = "hosc", "losc";
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	rtc: rtc@1c20400 {
	compatible = "allwinner,sun6i-a31-rtc";
	reg = <0x01c20400 0x54>;
	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	};

	pio: pinctrl@1c20800 {
	compatible = "allwinner,sun8i-v3s-pinctrl";
	reg = <0x01c20800 0x400>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
	clock-names = "apb", "hosc", "losc";
	gpio-controller;
	#gpio-cells = <3>;
	interrupt-controller;
	#interrupt-cells = <3>;

	i2c0_pins: i2c0 {
	pins = "PB6", "PB7";
	function = "i2c0";
	};

	uart0_pins_a: uart0@0 {
	pins = "PB8", "PB9";
	function = "uart0";
	};

	mmc0_pins_a: mmc0@0 {
	pins = "PF0", "PF1", "PF2", "PF3",
	"PF4", "PF5";
	function = "mmc0";
	drive-strength = <30>;
	bias-pull-up;
	};

	mmc1_pins: mmc1 {
	pins = "PG0", "PG1", "PG2", "PG3",
	"PG4", "PG5";
	function = "mmc1";
	drive-strength = <30>;
	bias-pull-up;
	};

	spi0_pins: spi0 {
	pins = "PC0", "PC1", "PC2", "PC3";
	function = "spi0";
	};
	};

	timer@1c20c00 {
	compatible = "allwinner,sun4i-a10-timer";
	reg = <0x01c20c00 0xa0>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc24M>;
	};

	wdt0: watchdog@1c20ca0 {
	compatible = "allwinner,sun6i-a31-wdt";
	reg = <0x01c20ca0 0x20>;
	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	};

	lradc: lradc@1c22800 {
	compatible = "allwinner,sun4i-a10-lradc-keys";
	reg = <0x01c22800 0x400>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	uart0: serial@1c28000 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28000 0x400>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART0>;
	resets = <&ccu RST_BUS_UART0>;
	status = "disabled";
	};

	uart1: serial@1c28400 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28400 0x400>;
	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART1>;
	resets = <&ccu RST_BUS_UART1>;
	status = "disabled";
	};

	uart2: serial@1c28800 {
	compatible = "snps,dw-apb-uart";
	reg = <0x01c28800 0x400>;
	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	clocks = <&ccu CLK_BUS_UART2>;
	resets = <&ccu RST_BUS_UART2>;
	status = "disabled";
	};

	i2c0: i2c@1c2ac00 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2ac00 0x400>;
	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C0>;
	resets = <&ccu RST_BUS_I2C0>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	i2c1: i2c@1c2b000 {
	compatible = "allwinner,sun6i-a31-i2c";
	reg = <0x01c2b000 0x400>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_I2C1>;
	resets = <&ccu RST_BUS_I2C1>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	spi0: spi@1c68000 {
	compatible = "allwinner,sun8i-h3-spi";
	reg = <0x01c68000 0x1000>;
	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
	clock-names = "ahb", "mod";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins>;
	resets = <&ccu RST_BUS_SPI0>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <0>;
	};

	gic: interrupt-controller@1c81000 {
	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	reg = <0x01c81000 0x1000>,
	<0x01c82000 0x1000>,
	<0x01c84000 0x2000>,
	<0x01c86000 0x2000>;
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};
	};
	};