1. 22f65a3 clk: meson: use SPDX license identifiers consistently by Jerome Brunet · 7 years ago
  2. b8c1dda clk: meson: meson8b: add support for the NAND clocks by Martin Blumenstingl · 7 years ago
  3. 05f8144 clk: meson: add fdiv clock gates by Jerome Brunet · 7 years ago
  4. 513b67a clk: meson: add mpll pre-divider by Jerome Brunet · 7 years ago
  5. 251b6fd clk: meson: rework meson8b cpu clock by Jerome Brunet · 7 years ago
  6. d610b54 clk: meson: split divider and gate part of mpll by Jerome Brunet · 7 years ago
  7. 1896217 clk: meson: meson8b: register the built-in reset controller by Martin Blumenstingl · 8 years ago
  8. 3112882 clk: meson8b: expose every clock in the bindings by Jerome Brunet · 8 years ago
  9. c22f06d clk: meson8b: export the ethernet gate clock by Martin Blumenstingl · 8 years ago
  10. 677f6af clk: meson8b: export the USB clocks by Martin Blumenstingl · 8 years ago
  11. 06eff6a clk: meson8b: export the gate clock for the HW random number generator by Martin Blumenstingl · 8 years ago
  12. e2e5f32 clk: meson8b: export the SDIO clock by Martin Blumenstingl · 8 years ago
  13. 70ad0d0 clk: meson8b: export the SAR ADC clocks by Martin Blumenstingl · 8 years ago
  14. b778f74 clk: meson8b: add the mplls clocks 0, 1 and 2 by Jerome Brunet · 8 years ago
  15. e31a190 meson: clk: Add support for clock gates by Alexander Müller · 9 years ago
  16. 0f32e64 clk: meson: Copy meson8b CLKID defines to private header file by Alexander Müller · 9 years ago
  17. e0818a3 meson: clk: Rename register names according to Amlogic datasheet by Alexander Müller · 9 years ago
  18. d0c175d meson: clk: Move register definitions to meson8b.h by Alexander Müller · 9 years ago