# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022-2023 Renesas Electronics Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car Gen4 PCIe Endpoint

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

allOf:
  - $ref: snps,dw-pcie-ep.yaml#

properties:
  compatible:
    items:
      - const: renesas,r8a779f0-pcie-ep   # R-Car S4-8
      - const: renesas,rcar-gen4-pcie-ep  # R-Car Gen4

  reg:
    maxItems: 7

  reg-names:
    items:
      - const: dbi
      - const: dbi2
      - const: atu
      - const: dma
      - const: app
      - const: phy
      - const: addr_space

  interrupts:
    maxItems: 3

  interrupt-names:
    items:
      - const: dma
      - const: sft_ce
      - const: app

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: core
      - const: ref

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: pwr

  max-link-speed:
    maximum: 4

  num-lanes:
    maximum: 4

  max-functions:
    maximum: 2

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - power-domains
  - resets
  - reset-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a779f0-sysc.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie0_ep: pcie-ep@e65d0000 {
            compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";
            reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
                  <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
                  <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
                  <0 0xfe000000 0 0x400000>;
            reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
            interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "dma", "sft_ce", "app";
            clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
            clock-names = "core", "ref";
            power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
            resets = <&cpg 624>;
            reset-names = "pwr";
            max-link-speed = <4>;
            num-lanes = <2>;
            max-functions = /bits/ 8 <2>;
        };
    };