[
    {
        "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.WALK_COMPLETED",
        "PEBScounters": "0,1,2,3,4,5,6,7",
        "SampleAfterValue": "200003",
        "UMask": "0xe",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "UMask": "0xe",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "UMask": "0xe",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
        "CollectPEBSRecord": "2",
        "Counter": "0,1,2,3",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.WALK_COMPLETED",
        "PEBScounters": "0,1,2,3",
        "SampleAfterValue": "100003",
        "UMask": "0xe",
        "Unit": "cpu_core"
    }
]