[
    {
        "ArchStdEvent": "MEM_ACCESS"
    },
    {
        "ArchStdEvent": "MEM_ACCESS_RD"
    },
    {
        "ArchStdEvent": "MEM_ACCESS_WR"
    },
    {
        "ArchStdEvent": "UNALIGNED_LDST_SPEC"
    }
]