# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC Bus and Interconnect

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  The Samsung Exynos SoC has many buses for data transfer between DRAM and
  sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
  Generally, each bus of Exynos SoC includes a source clock and a power line,
  which are able to change the clock frequency of the bus in runtime. To
  monitor the usage of each bus in runtime, the driver uses the PPMU (Platform
  Performance Monitoring Unit), which is able to measure the current load of
  sub-blocks.

  The Exynos SoC includes the various sub-blocks which have the each AXI bus.
  The each AXI bus has the owned source clock but, has not the only owned power
  line. The power line might be shared among one more sub-blocks.  So, we can
  divide into two type of device as the role of each sub-block.  There are two
  type of bus devices as following::
   - parent bus device
   - passive bus device

  Basically, parent and passive bus device share the same power line.  The
  parent bus device can only change the voltage of shared power line and the
  rest bus devices (passive bus device) depend on the decision of the parent
  bus device. If there are three blocks which share the VDD_xxx power line,
  Only one block should be parent device and then the rest blocks should depend
  on the parent device as passive device.

    VDD_xxx |--- A block (parent)
      |--- B block (passive)
      |--- C block (passive)

  There are a little different composition among Exynos SoC because each Exynos
  SoC has different sub-blocks. Therefore, such difference should be specified
  in devicetree file instead of each device driver. In result, this driver is
  able to support the bus frequency for all Exynos SoCs.

  Detailed correlation between sub-blocks and power line according
  to Exynos SoC::
   - In case of Exynos3250, there are two power line as following::
     VDD_MIF |--- DMC (Dynamic Memory Controller)

     VDD_INT |--- LEFTBUS (parent device)
       |--- PERIL
       |--- MFC
       |--- G3D
       |--- RIGHTBUS
       |--- PERIR
       |--- FSYS
       |--- LCD0
       |--- PERIR
       |--- ISP
       |--- CAM

     - MIF bus's frequency/voltage table
       -----------------------
       |Lv| Freq   | Voltage |
       -----------------------
       |L1| 50000  |800000   |
       |L2| 100000 |800000   |
       |L3| 134000 |800000   |
       |L4| 200000 |825000   |
       |L5| 400000 |875000   |
       -----------------------

     - INT bus's frequency/voltage table
       ----------------------------------------------------------
       |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |
       | name|       |LCD0    |       |       |       ||        |
       |     |       |FSYS    |       |       |       ||        |
       |     |       |MFC     |       |       |       ||        |
       ----------------------------------------------------------
       |Mode |*parent|passive |passive|passive|passive||        |
       ----------------------------------------------------------
       |Lv   |Frequency                               ||Voltage |
       ----------------------------------------------------------
       |L1   |50000  |50000   |50000  |50000  |50000  ||900000  |
       |L2   |80000  |80000   |80000  |80000  |80000  ||900000  |
       |L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |
       |L4   |134000 |134000  |200000 |200000 |       ||1000000 |
       |L5   |200000 |200000  |400000 |300000 |       ||1000000 |
       ----------------------------------------------------------

   - In case of Exynos4210, there is one power line as following::
     VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
       |--- LEFTBUS
       |--- PERIL
       |--- MFC(L)
       |--- G3D
       |--- TV
       |--- LCD0
       |--- RIGHTBUS
       |--- PERIR
       |--- MFC(R)
       |--- CAM
       |--- FSYS
       |--- GPS
       |--- LCD0
       |--- LCD1

   - In case of Exynos4x12, there are two power line as following::
     VDD_MIF |--- DMC (Dynamic Memory Controller)

     VDD_INT |--- LEFTBUS (parent device)
       |--- PERIL
       |--- MFC(L)
       |--- G3D
       |--- TV
       |--- IMAGE
       |--- RIGHTBUS
       |--- PERIR
       |--- MFC(R)
       |--- CAM
       |--- FSYS
       |--- GPS
       |--- LCD0
       |--- ISP

   - In case of Exynos5422, there are two power line as following::
     VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
             |--- DREX 1

     VDD_INT |--- NoC_Core (parent device)
       |--- G2D
       |--- G3D
       |--- DISP1
       |--- NoC_WCORE
       |--- GSCL
       |--- MSCL
       |--- ISP
       |--- MFC
       |--- GEN
       |--- PERIS
       |--- PERIC
       |--- FSYS
       |--- FSYS2

   - In case of Exynos5433, there is VDD_INT power line as following::
     VDD_INT |--- G2D (parent device)
       |--- MSCL
       |--- GSCL
       |--- JPEG
       |--- MFC
       |--- HEVC
       |--- BUS0
       |--- BUS1
       |--- BUS2
       |--- PERIS (Fixed clock rate)
       |--- PERIC (Fixed clock rate)
       |--- FSYS  (Fixed clock rate)

properties:
  compatible:
    enum:
      - samsung,exynos-bus

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: bus

  devfreq:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Parent bus device. Valid and required only for the passive bus devices.

  devfreq-events:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 1
    maxItems: 4
    description:
      Devfreq-event device to monitor the current utilization of buses. Valid
      and required only for the parent bus devices.

  exynos,saturation-ratio:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Percentage value which is used to calibrate the performance count against
      total cycle count.  Valid only for the parent bus devices.

  '#interconnect-cells':
    const: 0

  interconnects:
    minItems: 1
    maxItems: 2

  operating-points-v2: true

  samsung,data-clock-ratio:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 8
    description:
      Ratio of the data throughput in B/s to minimum data clock frequency in
      Hz.

  vdd-supply:
    description:
      Main bus power rail. Valid and required only for the parent bus devices.

required:
  - compatible
  - clocks
  - clock-names
  - operating-points-v2

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos3250.h>

    bus-dmc {
        compatible = "samsung,exynos-bus";
        clocks = <&cmu_dmc CLK_DIV_DMC>;
        clock-names = "bus";
        operating-points-v2 = <&bus_dmc_opp_table>;
        devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
        vdd-supply = <&buck1_reg>;
    };

    ppmu_dmc0: ppmu@106a0000 {
        compatible = "samsung,exynos-ppmu";
        reg = <0x106a0000 0x2000>;
        events {
            ppmu_dmc0_3: ppmu-event3-dmc0 {
                event-name = "ppmu-event3-dmc0";
            };
        };
    };

    bus_leftbus: bus-leftbus {
        compatible = "samsung,exynos-bus";
        clocks = <&cmu CLK_DIV_GDL>;
        clock-names = "bus";
        operating-points-v2 = <&bus_leftbus_opp_table>;
        devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
        vdd-supply = <&buck3_reg>;
    };

    bus-rightbus {
        compatible = "samsung,exynos-bus";
        clocks = <&cmu CLK_DIV_GDR>;
        clock-names = "bus";
        operating-points-v2 = <&bus_leftbus_opp_table>;
        devfreq = <&bus_leftbus>;
    };

  - |
    dmc: bus-dmc {
        compatible = "samsung,exynos-bus";
        clocks = <&clock CLK_DIV_DMC>;
        clock-names = "bus";
        operating-points-v2 = <&bus_dmc_opp_table>;
        samsung,data-clock-ratio = <4>;
        #interconnect-cells = <0>;
        devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
        vdd-supply = <&buck1_reg>;
    };

    leftbus: bus-leftbus {
        compatible = "samsung,exynos-bus";
        clocks = <&clock CLK_DIV_GDL>;
        clock-names = "bus";
        operating-points-v2 = <&bus_leftbus_opp_table>;
        interconnects = <&dmc>;
        #interconnect-cells = <0>;
        devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
        vdd-supply = <&buck3_reg>;
    };

    display: bus-display {
        compatible = "samsung,exynos-bus";
        clocks = <&clock CLK_DIV_ACLK_266>;
        clock-names = "bus";
        operating-points-v2 = <&bus_display_opp_table>;
        interconnects = <&leftbus &dmc>;
        #interconnect-cells = <0>;
        devfreq = <&leftbus>;
    };