arch/arm64/boot/dts/freescale/imx943.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2025 NXP
 */

#include "imx94.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		idle-states {
			entry-method = "psci";

			cpu_pd_wait: cpu-pd-wait {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010033>;
				local-timer-stop;
				entry-latency-us = <1000>;
				exit-latency-us = <700>;
				min-residency-us = <2700>;
				wakeup-latency-us = <1500>;
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x0>;
			enable-method = "psci";
			#cooling-cells = <2>;
			cpu-idle-states = <&cpu_pd_wait>;
			power-domains = <&scmi_perf IMX94_PERF_A55>;
			power-domain-names = "perf";
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache_l0>;
		};

		cpu1: cpu@100 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x100>;
			enable-method = "psci";
			#cooling-cells = <2>;
			cpu-idle-states = <&cpu_pd_wait>;
			power-domains = <&scmi_perf IMX94_PERF_A55>;
			power-domain-names = "perf";
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache_l1>;
		};

		cpu2: cpu@200 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x200>;
			enable-method = "psci";
			#cooling-cells = <2>;
			cpu-idle-states = <&cpu_pd_wait>;
			power-domains = <&scmi_perf IMX94_PERF_A55>;
			power-domain-names = "perf";
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache_l2>;
		};

		cpu3: cpu@300 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x300>;
			enable-method = "psci";
			#cooling-cells = <2>;
			cpu-idle-states = <&cpu_pd_wait>;
			power-domains = <&scmi_perf IMX94_PERF_A55>;
			power-domain-names = "perf";
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache_l3>;
		};

		l2_cache_l0: l2-cache-l0 {
			compatible = "cache";
			cache-size = <65536>;
			cache-line-size = <64>;
			cache-sets = <256>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_l1: l2-cache-l1 {
			compatible = "cache";
			cache-size = <65536>;
			cache-line-size = <64>;
			cache-sets = <256>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_l2: l2-cache-l2 {
			compatible = "cache";
			cache-size = <65536>;
			cache-line-size = <64>;
			cache-sets = <256>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_l3: l2-cache-l3 {
			compatible = "cache";
			cache-size = <65536>;
			cache-line-size = <64>;
			cache-sets = <256>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l3_cache: l3-cache {
			compatible = "cache";
			cache-size = <1048576>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-level = <3>;
			cache-unified;
		};
	};
};