Mediatek Video Encoder

Mediatek Video Encoder is the video encode hw present in Mediatek SoCs which
supports high resolution encoding functionalities.

Required properties:
- compatible : must be one of the following string:
  "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder.
  "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
  "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
  "mediatek,mt8192-vcodec-enc" for MT8192 encoder.
- reg : Physical base address of the video encoder registers and length of
  memory mapped region.
- interrupts : interrupt number to the cpu.
- mediatek,larb : must contain the local arbiters in the current Socs.
- clocks : list of clock specifiers, corresponding to entries in
  the clock-names property.
- clock-names: avc encoder must contain "venc_sel", vp8 encoder must
  contain "venc_lt_sel", decoder must contain "vcodecpll", "univpll_d2",
  "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel",
  "vdec_bus_clk_src".
- iommus : should point to the respective IOMMU block with master port as
  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
  for details.
- dma-ranges : describes how the physical address space of the IOMMU maps
  to memory.
One of the two following nodes:
- mediatek,vpu : the node of the video processor unit, if using VPU.
- mediatek,scp : the node of the SCP unit, if using SCP.


Example:

vcodec_enc_avc: vcodec@18002000 {
    compatible = "mediatek,mt8173-vcodec-enc";
    reg = <0 0x18002000 0 0x1000>;
    interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
    iommus = <&iommu M4U_PORT_VENC_RCPU>,
             <&iommu M4U_PORT_VENC_REC>,
             <&iommu M4U_PORT_VENC_BSDMA>,
             <&iommu M4U_PORT_VENC_SV_COMV>,
             <&iommu M4U_PORT_VENC_RD_COMV>,
             <&iommu M4U_PORT_VENC_CUR_LUMA>,
             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
             <&iommu M4U_PORT_VENC_REF_LUMA>,
             <&iommu M4U_PORT_VENC_REF_CHROMA>,
             <&iommu M4U_PORT_VENC_NBM_RDMA>,
             <&iommu M4U_PORT_VENC_NBM_WDMA>;
    mediatek,larb = <&larb3>;
    mediatek,vpu = <&vpu>;
    clocks = <&topckgen CLK_TOP_VENC_SEL>;
    clock-names = "venc_sel";
    assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
  };

vcodec_enc_vp8: vcodec@19002000 {
    compatible = "mediatek,mt8173-vcodec-enc-vp8";
    reg =  <0 0x19002000 0 0x1000>;	/* VENC_LT_SYS */
    interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
    iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
    mediatek,larb = <&larb5>;
    mediatek,vpu = <&vpu>;
    clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
    clock-names = "venc_lt_sel";
    assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
  };