/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
/*
 * Copyright (c) 2021 MediaTek Inc.
 * Author: Christine Zhu <christine.zhu@mediatek.com>
 */

#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
#define _DT_BINDINGS_RESET_CONTROLLER_MT8195

#define MT8195_TOPRGU_CONN_MCU_SW_RST          0
#define MT8195_TOPRGU_INFRA_GRST_SW_RST        1
#define MT8195_TOPRGU_APU_SW_RST               2
#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST     6
#define MT8195_TOPRGU_MMSYS_SW_RST             7
#define MT8195_TOPRGU_MFG_SW_RST               8
#define MT8195_TOPRGU_VENC_SW_RST              9
#define MT8195_TOPRGU_VDEC_SW_RST              10
#define MT8195_TOPRGU_IMG_SW_RST               11
#define MT8195_TOPRGU_APMIXEDSYS_SW_RST        13
#define MT8195_TOPRGU_AUDIO_SW_RST             14
#define MT8195_TOPRGU_CAMSYS_SW_RST            15
#define MT8195_TOPRGU_EDPTX_SW_RST             16
#define MT8195_TOPRGU_ADSPSYS_SW_RST           21
#define MT8195_TOPRGU_DPTX_SW_RST              22
#define MT8195_TOPRGU_SPMI_MST_SW_RST          23

#define MT8195_TOPRGU_SW_RST_NUM               24

/* VDOSYS1 */
#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC          25
#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC          26
#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC          27
#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC          28
#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC          29
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC     51
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC     52
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC     53
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC     54
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC      55

#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */