# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mutex.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek mutex

maintainers:
  - Matthias Brugger <matthias.bgg@gmail.com>

description: |
  MediaTek mutex, namely MUTEX, is used to send the triggers signals called
  Start Of Frame(SOF) / End Of Frame(EOF) to each sub-modules on the data path.
  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
  the shadow register.
  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt2701-disp-mutex
      - items:
          - const: mediatek,mt2712-disp-mutex
      - items:
          - const: mediatek,mt8167-disp-mutex
      - items:
          - const: mediatek,mt8173-disp-mutex
      - items:
          - const: mediatek,mt8183-disp-mutex
      - items:
          - const: mediatek,mt8192-disp-mutex
      - items:
          - const: mediatek,mt8195-disp-mutex
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: MUTEX Clock

  mediatek,gce-events:
    description:
      The event id which is mapping to the specific hardware event signal
      to gce. The event id is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h of each chips.
    $ref: /schemas/types.yaml#/definitions/phandle-array

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |

    mutex: mutex@14020000 {
        compatible = "mediatek,mt8173-disp-mutex";
        reg = <0 0x14020000 0 0x1000>;
        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
        clocks = <&mmsys CLK_MM_MUTEX_32K>;
        mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
                              <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
    };