# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,ccorr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek color correction

maintainers:
  - Matthias Brugger <matthias.bgg@gmail.com>

description: |
  MediaTek color correction, namely CCORR, reproduces correct color
  on panels with different color gamut.
  CCORR device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt8183-disp-ccorr
      - items:
          - const: mediatek,mt8192-disp-ccorr
      - items:
          - enum:
              - mediatek,mt8195-disp-ccorr
          - enum:
              - mediatek,mt8192-disp-ccorr

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: CCORR Clock

  mediatek,gce-client-reg:
    description:
      The register of client driver can be configured by gce with 4 arguments
      defined in this property, such as phandle of gce, subsys id,
      register offset and size.
      Each subsys id is mapping to a base address of display function blocks
      register which is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |

    ccorr0: ccorr@1400f000 {
        compatible = "mediatek,mt8183-disp-ccorr";
        reg = <0 0x1400f000 0 0x1000>;
        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
        clocks = <&mmsys CLK_MM_DISP_CCORR0>;
        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
    };