# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek AFE PCM controller for mt8192

maintainers:
   - Jiaxin Yu <jiaxin.yu@mediatek.com>
   - Shane Chien <shane.chien@mediatek.com>

properties:
  compatible:
      const: mediatek,mt8192-audio

  interrupts:
    maxItems: 1

  resets:
    maxItems: 1

  reset-names:
    const: audiosys

  mediatek,apmixedsys:
    $ref: "/schemas/types.yaml#/definitions/phandle"
    description: The phandle of the mediatek apmixedsys controller

  mediatek,infracfg:
    $ref: "/schemas/types.yaml#/definitions/phandle"
    description: The phandle of the mediatek infracfg controller

  mediatek,topckgen:
    $ref: "/schemas/types.yaml#/definitions/phandle"
    description: The phandle of the mediatek topckgen controller

  power-domains:
    maxItems: 1

  clocks:
    items:
      - description: AFE clock
      - description: ADDA DAC clock
      - description: ADDA DAC pre-distortion clock
      - description: audio infra sys clock
      - description: audio infra 26M clock

  clock-names:
    items:
      - const: aud_afe_clk
      - const: aud_dac_clk
      - const: aud_dac_predis_clk
      - const: aud_infra_clk
      - const: aud_infra_26m_clk

required:
  - compatible
  - interrupts
  - resets
  - reset-names
  - mediatek,apmixedsys
  - mediatek,infracfg
  - mediatek,topckgen
  - power-domains
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8192-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/mt8192-power.h>
    #include <dt-bindings/reset-controller/mt8192-resets.h>

    afe: mt8192-afe-pcm {
        compatible = "mediatek,mt8192-audio";
        interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
        resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
        reset-names = "audiosys";
        mediatek,apmixedsys = <&apmixedsys>;
        mediatek,infracfg = <&infracfg>;
        mediatek,topckgen = <&topckgen>;
        power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
        clocks = <&audsys CLK_AUD_AFE>,
                 <&audsys CLK_AUD_DAC>,
                 <&audsys CLK_AUD_DAC_PREDIS>,
                 <&infracfg CLK_INFRA_AUDIO>,
                 <&infracfg CLK_INFRA_AUDIO_26M_B>;
        clock-names = "aud_afe_clk",
                      "aud_dac_clk",
                      "aud_dac_predis_clk",
                      "aud_infra_clk",
                      "aud_infra_26m_clk";
    };

...