// SPDX-License-Identifier: GPL-2.0
/*
 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
 *
 * Copyright (C) 2018 Renesas Electronics Europe Limited
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>

/ {
	compatible = "renesas,r9a06g032";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
			enable-method = "renesas,r9a06g032-smp";
			cpu-release-addr = <0 0x4000c204>;
		};
	};

	ext_jtag_clk: extjtagclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	ext_mclk: extmclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <40000000>;
	};

	ext_rgmii_ref: extrgmiiref {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	ext_rtc_clk: extrtcclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;
		ranges;

		rtc0: rtc@40006000 {
			compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
			reg = <0x40006000 0x1000>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "alarm", "timer", "pps";
			clocks = <&sysctrl R9A06G032_HCLK_RTC>;
			clock-names = "hclk";
			power-domains = <&sysctrl>;
			status = "disabled";
		};

		wdt0: watchdog@40008000 {
			compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
			reg = <0x40008000 0x1000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
			clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
			status = "disabled";
		};

		wdt1: watchdog@40009000 {
			compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
			reg = <0x40009000 0x1000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
			clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
			status = "disabled";
		};

		sysctrl: system-controller@4000c000 {
			compatible = "renesas,r9a06g032-sysctrl";
			reg = <0x4000c000 0x1000>;
			status = "okay";
			#clock-cells = <1>;
			#power-domain-cells = <0>;

			clocks = <&ext_mclk>, <&ext_rtc_clk>,
					<&ext_jtag_clk>, <&ext_rgmii_ref>;
			clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
			#address-cells = <1>;
			#size-cells = <1>;

			dmamux: dma-router@a0 {
				compatible = "renesas,rzn1-dmamux";
				reg = <0xa0 4>;
				#dma-cells = <6>;
				dma-requests = <32>;
				dma-masters = <&dma0 &dma1>;
			};
		};

		pci_usb: pci@40030000 {
			compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
			device_type = "pci";
			clocks = <&sysctrl R9A06G032_HCLK_USBH>,
				 <&sysctrl R9A06G032_HCLK_USBPM>,
				 <&sysctrl R9A06G032_CLK_PCI_USB>;
			clock-names = "hclkh", "hclkpm", "pciclk";
			power-domains = <&sysctrl>;
			reg = <0x40030000 0xc00>,
			      <0x40020000 0x1100>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";

			bus-range = <0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
			/* Should map all possible DDR as inbound ranges, but
			 * the IP only supports a 256MB, 512MB, or 1GB window.
			 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
			 */
			dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
			interrupt-map-mask = <0xf800 0 0 0x7>;
			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
					 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
					 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;

			usb@1,0 {
				reg = <0x800 0 0 0 0>;
				phys = <&usbphy>;
				phy-names = "usb";
			};

			usb@2,0 {
				reg = <0x1000 0 0 0 0>;
				phys = <&usbphy>;
				phy-names = "usb";
			};
		};

		uart0: serial@40060000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40060000 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart1: serial@40061000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40061000 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart2: serial@40062000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40062000 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart3: serial@50000000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50000000 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
			clock-names = "baudclk", "apb_pclk";
			dmas =  <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart4: serial@50001000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50001000 0x400>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
			clock-names = "baudclk", "apb_pclk";
			dmas =  <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart5: serial@50002000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50002000 0x400>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
			clock-names = "baudclk", "apb_pclk";
			dmas =  <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart6: serial@50003000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50003000 0x400>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
			clock-names = "baudclk", "apb_pclk";
			dmas =  <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart7: serial@50004000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50004000 0x400>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
			clock-names = "baudclk", "apb_pclk";
			dmas =  <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		pinctrl: pinctrl@40067000 {
			compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
			reg = <0x40067000 0x1000>, <0x51000000 0x480>;
			clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
			clock-names = "bus";
			status = "okay";
		};

		nand_controller: nand-controller@40102000 {
			compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
			reg = <0x40102000 0x2000>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
			clock-names = "hclk", "eclk";
			power-domains = <&sysctrl>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		dma0: dma-controller@40104000 {
			compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
			reg = <0x40104000 0x1000>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "hclk";
			clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
			dma-channels = <8>;
			dma-requests = <16>;
			dma-masters = <1>;
			#dma-cells = <3>;
			block_size = <0xfff>;
			data-width = <8>;
		};

		dma1: dma-controller@40105000 {
			compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
			reg = <0x40105000 0x1000>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "hclk";
			clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
			dma-channels = <8>;
			dma-requests = <16>;
			dma-masters = <1>;
			#dma-cells = <3>;
			block_size = <0xfff>;
			data-width = <8>;
		};

		gmac2: ethernet@44002000 {
			compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
			reg = <0x44002000 0x2000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
			clocks = <&sysctrl R9A06G032_HCLK_GMAC1>;
			clock-names = "stmmaceth";
			power-domains = <&sysctrl>;
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <2048>;
			rx-fifo-depth = <4096>;
			status = "disabled";
		};

		eth_miic: eth-miic@44030000 {
			compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x44030000 0x10000>;
			clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
				 <&sysctrl R9A06G032_CLK_RGMII_REF>,
				 <&sysctrl R9A06G032_CLK_RMII_REF>,
				 <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
			clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
			power-domains = <&sysctrl>;
			status = "disabled";

			mii_conv1: mii-conv@1 {
				reg = <1>;
				status = "disabled";
			};

			mii_conv2: mii-conv@2 {
				reg = <2>;
				status = "disabled";
			};

			mii_conv3: mii-conv@3 {
				reg = <3>;
				status = "disabled";
			};

			mii_conv4: mii-conv@4 {
				reg = <4>;
				status = "disabled";
			};

			mii_conv5: mii-conv@5 {
				reg = <5>;
				status = "disabled";
			};
		};

		switch: switch@44050000 {
			compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
			reg = <0x44050000 0x10000>;
			clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
				 <&sysctrl R9A06G032_CLK_SWITCH>;
			clock-names = "hclk", "clk";
			power-domains = <&sysctrl>;
			status = "disabled";

			ethernet-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				switch_port0: port@0 {
					reg = <0>;
					pcs-handle = <&mii_conv5>;
					status = "disabled";
				};

				switch_port1: port@1 {
					reg = <1>;
					pcs-handle = <&mii_conv4>;
					status = "disabled";
				};

				switch_port2: port@2 {
					reg = <2>;
					pcs-handle = <&mii_conv3>;
					status = "disabled";
				};

				switch_port3: port@3 {
					reg = <3>;
					pcs-handle = <&mii_conv2>;
					status = "disabled";
				};

				switch_port4: port@4 {
					reg = <4>;
					ethernet = <&gmac2>;
					label = "cpu";
					phy-mode = "internal";
					status = "disabled";
					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};
			};
		};

		gic: interrupt-controller@44101000 {
			compatible = "arm,gic-400", "arm,cortex-a7-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x44101000 0x1000>, /* Distributer */
			      <0x44102000 0x2000>, /* CPU interface */
			      <0x44104000 0x2000>, /* Virt interface control */
			      <0x44106000 0x2000>; /* Virt CPU interface */
			interrupts =
				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		arm,cpu-registers-not-fw-configured;
		always-on;
		interrupts =
			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	usbphy: usb-phy {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
		status = "disabled";
	};
};