Mediatek display subsystem
==========================

The Mediatek display subsystem consists of various DISP function blocks in the
MMSYS register space. The connections between them can be configured by output
and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
of frame signal are distributed to the other function blocks by a DISP_MUTEX
function block.

All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
For a description of the MMSYS_CONFIG binding, see
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.

DISP function blocks
====================

A display stream starts at a source function block that reads pixel data from
memory and ends with a sink function block that drives pixels on a display
interface, or writes pixels back to memory. All DISP function blocks have
their own register space, interrupt, and clock gate. The blocks that can
access memory additionally have to list the IOMMU and local arbiter they are
connected to.

For a description of the display interface sink function blocks, see
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.

Required properties (all function blocks):
- compatible: "mediatek,<chip>-disp-<function>", one of
	"mediatek,<chip>-disp-ovl"   		- overlay (4 layers, blending, csc)
	"mediatek,<chip>-disp-ovl-2l"           - overlay (2 layers, blending, csc)
	"mediatek,<chip>-disp-rdma"  		- read DMA / line buffer
	"mediatek,<chip>-disp-wdma"  		- write DMA
	"mediatek,<chip>-disp-ccorr"            - color correction
	"mediatek,<chip>-disp-color" 		- color processor
	"mediatek,<chip>-disp-dither"           - dither
	"mediatek,<chip>-disp-aal"   		- adaptive ambient light controller
	"mediatek,<chip>-disp-gamma" 		- gamma correction
	"mediatek,<chip>-disp-merge" 		- merge streams from two RDMA sources
	"mediatek,<chip>-disp-postmask" 	- control round corner for display frame
	"mediatek,<chip>-disp-split" 		- split stream to two encoders
	"mediatek,<chip>-disp-ufoe"  		- data compression engine
	"mediatek,<chip>-dsi"        		- DSI controller, see mediatek,dsi.txt
	"mediatek,<chip>-dpi"        		- DPI controller, see mediatek,dpi.txt
	"mediatek,<chip>-disp-mutex" 		- display mutex
	"mediatek,<chip>-disp-od"    		- overdrive
  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
- reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for
  merge and split function blocks).
- clocks: device clocks
  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
  For most function blocks this is just a single clock input. Only the DSI and
  DPI controller nodes have multiple clock inputs. These are documented in
  mediatek,dsi.txt and mediatek,dpi.txt, respectively.
  An exception is that the mt8183 mutex is always free running with no clocks property.

Required properties (DMA function blocks):
- compatible: Should be one of
	"mediatek,<chip>-disp-ovl"
	"mediatek,<chip>-disp-rdma"
	"mediatek,<chip>-disp-wdma"
  the supported chips are mt2701, mt8167 and mt8173.
- larb: Should contain a phandle pointing to the local arbiter device as defined
  in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
- iommus: Should point to the respective IOMMU block with master port as
  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
  for details.

Optional properties (RDMA function blocks):
- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
  property to the corresponding rdma
  the value is the Max value which defined in hardware data sheet.
  mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
  mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
  mediatek,rdma-fifo-size of mt8183-rdma1 is 2K

Examples:

mmsys: clock-controller@14000000 {
	compatible = "mediatek,mt8173-mmsys", "syscon";
	reg = <0 0x14000000 0 0x1000>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	#clock-cells = <1>;
};

ovl0: ovl@1400c000 {
	compatible = "mediatek,mt8173-disp-ovl";
	reg = <0 0x1400c000 0 0x1000>;
	interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_OVL0>;
	iommus = <&iommu M4U_PORT_DISP_OVL0>;
	mediatek,larb = <&larb0>;
};

ovl1: ovl@1400d000 {
	compatible = "mediatek,mt8173-disp-ovl";
	reg = <0 0x1400d000 0 0x1000>;
	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_OVL1>;
	iommus = <&iommu M4U_PORT_DISP_OVL1>;
	mediatek,larb = <&larb4>;
};

rdma0: rdma@1400e000 {
	compatible = "mediatek,mt8173-disp-rdma";
	reg = <0 0x1400e000 0 0x1000>;
	interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_RDMA0>;
	iommus = <&iommu M4U_PORT_DISP_RDMA0>;
	mediatek,larb = <&larb0>;
	mediatek,rdma-fifosize = <8192>;
};

rdma1: rdma@1400f000 {
	compatible = "mediatek,mt8173-disp-rdma";
	reg = <0 0x1400f000 0 0x1000>;
	interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_RDMA1>;
	iommus = <&iommu M4U_PORT_DISP_RDMA1>;
	mediatek,larb = <&larb4>;
};

rdma2: rdma@14010000 {
	compatible = "mediatek,mt8173-disp-rdma";
	reg = <0 0x14010000 0 0x1000>;
	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_RDMA2>;
	iommus = <&iommu M4U_PORT_DISP_RDMA2>;
	mediatek,larb = <&larb4>;
};

wdma0: wdma@14011000 {
	compatible = "mediatek,mt8173-disp-wdma";
	reg = <0 0x14011000 0 0x1000>;
	interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_WDMA0>;
	iommus = <&iommu M4U_PORT_DISP_WDMA0>;
	mediatek,larb = <&larb0>;
};

wdma1: wdma@14012000 {
	compatible = "mediatek,mt8173-disp-wdma";
	reg = <0 0x14012000 0 0x1000>;
	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_WDMA1>;
	iommus = <&iommu M4U_PORT_DISP_WDMA1>;
	mediatek,larb = <&larb4>;
};

color0: color@14013000 {
	compatible = "mediatek,mt8173-disp-color";
	reg = <0 0x14013000 0 0x1000>;
	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_COLOR0>;
};

color1: color@14014000 {
	compatible = "mediatek,mt8173-disp-color";
	reg = <0 0x14014000 0 0x1000>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_COLOR1>;
};

aal@14015000 {
	compatible = "mediatek,mt8173-disp-aal";
	reg = <0 0x14015000 0 0x1000>;
	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_AAL>;
};

gamma@14016000 {
	compatible = "mediatek,mt8173-disp-gamma";
	reg = <0 0x14016000 0 0x1000>;
	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_GAMMA>;
};

ufoe@1401a000 {
	compatible = "mediatek,mt8173-disp-ufoe";
	reg = <0 0x1401a000 0 0x1000>;
	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_UFOE>;
};

dsi0: dsi@1401b000 {
	/* See mediatek,dsi.txt for details */
};

dpi0: dpi@1401d000 {
	/* See mediatek,dpi.txt for details */
};

mutex: mutex@14020000 {
	compatible = "mediatek,mt8173-disp-mutex";
	reg = <0 0x14020000 0 0x1000>;
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_MUTEX_32K>;
};

od@14023000 {
	compatible = "mediatek,mt8173-disp-od";
	reg = <0 0x14023000 0 0x1000>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	clocks = <&mmsys CLK_MM_DISP_OD>;
};